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公开(公告)号：US5818276A
公开(公告)日：1998-10-06
申请号：US610178
申请日：1996-03-04
CPC分类号： H03K5/1515
摘要： A non-inverting, inverting, delayed non-inverting, and delayed inverting non-overlapping clock signal is provided by a non-overlapping clock generator circuit (41, 61). The non-overlapping clock generator circuit (41, 61) increases time for circuit operation by minimizing delays between non-overlapping clock signals and simultaneously transitioning rising edges of clock signals. A non-overlapping clock generation circuit (41) comprises six NOR gates (43-48) and an inverter (42). Three NOR gates form a first delay line (43-45) and the remaining three NOR gates form a second delay line (46-48). The inverter (42) provides an inverted clock signal to the second delay line. A clock signal propagates through one delay line while the other delay line is non-responsive due to a feedback signal from the active delay line. Once the clock signal has propagated through the active delay line, the feedback signal changes and allows NOR gates of the remaining delay line to simultaneously provide a clock signal and a delayed clock signal.
摘要翻译： 由非重叠时钟发生器电路（41,61）提供非反相，反相，延迟的非反相和延迟的反相非重叠时钟信号。 不重叠的时钟发生器电路（41,61）通过最小化不重叠的时钟信号之间的延迟并同时转换时钟信号的上升沿来增加电路操作的时间。 非重叠时钟产生电路（41）包括六个或非门（43-48）和一个反相器（42）。 三个或非门形成第一延迟线（43-45），其余三个或非门形成第二延迟线（46-48）。 反相器（42）向第二延迟线提供反相时钟信号。 时钟信号通过一个延迟线传播，而另一个延迟线由于来自有源延迟线的反馈信号而不响应。 一旦时钟信号已经通过有源延迟线传播，反馈信号改变并允许剩余延迟线的“或非”门同时提供时钟信号和延迟的时钟信号。
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公开(公告)号：US5894284A
公开(公告)日：1999-04-13
申请号：US753812
申请日：1996-12-02
CPC分类号： H03F3/005 , H03F3/45479 , H03M1/442
摘要： A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P.sub.1) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (V.sub.AGO) during a second clock phase, which increases the output loading during the second clock phase (P.sub.2). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P.sub.1) to match the load produced by the refresh circuit (604) during the second clock phase (P.sub.2).
摘要翻译： 时钟差分放大器（602）的共模感测电路（504）包括刷新电路（604），其在第一时钟相位（P1）期间对电容进行预充电，并且将电容放电以驱动输出（514,516）的 差分放大器（602）在第二时钟相位期间达到期望的共模电压（VAGO），这增加了在第二时钟相位（P2）期间的输出负载。 负载平衡电路（606）在第一时钟相位（P1）期间选择性地将负载切换到输出（514,516）以匹配在第二时钟相位（P2）期间由刷新电路（604）产生的负载。
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公开(公告)号：US5574457A
公开(公告)日：1996-11-12
申请号：US489349
申请日：1995-06-12
CPC分类号： H03M1/442 , H03F3/005 , H03H19/004
摘要： A switched capacitor gain stage (21) that samples an input voltage every clock cycle phase for effectively doubling the frequency of operation. The switched capacitor gain stage (21) comprising an amplifier (22), a first capacitor network, and a second capacitor network. Either the first or second capacitor network is sampling an input voltage. For example, the first capacitor network samples an input voltage. Capacitors of the first capacitor network are coupled to sample the input voltage via switches. Capacitors of the second switched capacitor network are coupled around the amplifier (22) in a gain configuration via switches. The capacitors of the second switched capacitor network having a voltage stored from a previous clock phase. In a next clock phase the second switched capacitor network are coupled via switches for sampling an input voltage and the first switched capacitor network is coupled via switches in a gain configuration around the amplifier (22).
摘要翻译： 开关电容器增益级（21），每个时钟周期阶段对输入电压进行采样，以有效地加倍工作频率。 开关电容器增益级（21）包括放大器（22），第一电容器网络和第二电容器网络。 第一或第二电容器网络都要对输入电压进行采样。 例如，第一电容器网络对输入电压进行采样。 第一电容器网络的电容器被耦合以通过开关对输入电压进行采样。 第二开关电容器网络的电容器通过开关以增益配置耦合在放大器（22）周围。 第二开关电容器网络的电容器具有从先前时钟相位存储的电压。 在下一个时钟阶段，第二开关电容器网络通过用于对输入电压进行采样的开关耦合，并且第一开关电容器网络通过放大器（22）周围的增益配置的开关耦合。
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公开(公告)号：US5644313A
公开(公告)日：1997-07-01
申请号：US463818
申请日：1995-06-05
CPC分类号： H03M1/403 , H03M1/0682
摘要： RSD n-bit analog-to-digital converter (10) receives voltage VIN that is compared to reference voltages VH and VL in the first stage (18). A digital code, representing VIN, is generated at first stage outputs (24, 26). First stage residue voltage V22 is compared to VH and VL in the second stage (30). A digital code generated at the outputs (28, 32) of the second stage, represent residue voltage V22. Residue voltage V22 is recycled through the first and second stages. Upon reaching the n.sup.th conversion bit, residue voltage V22 of the n.sup.th -1 bit is compared to second stage mid-level voltage reference VMID. A digital code generated at the outputs of the second stage represents the n.sup.th -1 bit residue voltage V22. The digital codes are stored in storage elements (34) and added in a binary adder (38) to provide the n-bit representation of VIN.
摘要翻译： RSD n位模数转换器（10）接收与第一级（18）中的参考电压VH和VL相比较的电压VIN。 代表VIN的数字代码在第一级输出（24,26）产生。 将第一级残留电压V22与第二级（30）中的VH和VL进行比较。 在第二级的输出端（28,32）产生的数字码表示残留电压V22。 残余电压V22通过第一和第二阶段再循环。 在到达第n个转换位时，将第n-1位的残余电压V22与第二级中间电平参考VMID进行比较。 在第二级的输出处产生的数字代码表示第n位残留电压V22。 数字代码被存储在存储元件（34）中并被加到二进制加法器（38）中以提供VIN的n位表示。
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5.发明授权Current source for reducing noise glitches generated in a digital to analog converter and method therefor 失效用于减少数模转换器中产生的噪声毛刺的电流源及其方法
公开(公告)号：US5625360A
公开(公告)日：1997-04-29
申请号：US524095
申请日：1995-09-05
CPC分类号： H03M1/0863 , H03M1/662 , H03M1/742
摘要： A switchable current source (41) for a Digital to Analog Converter (DAC) to reduce noise glitches when a change in total current provided by the DAC occurs. The switchable current source (41) is one of many required by a DAC to convert a digital signal to an analog signal. Each current source of the DAC receives an input voltage that enables or disables the current source from providing or not providing a current. A sampled input voltage is alternately provided to the switchable current source (41) by a first flip flop (42) or a second flip flop (43). One flip flop samples the input voltage while the other provides a previous sampled input voltage for enabling and disabling the switchable current source (41). Switches (46,47) couple an output voltage of the first or second flip flops (42,43) a predetermined time after the output voltage changes to a transistor (51) coupled to a current source (53).
摘要翻译： 用于数模转换器（DAC）的可切换电流源（41），用于在发生DAC提供的总电流变化时减少噪声毛刺。 可切换电流源（41）是DAC将数字信号转换为模拟信号的许多要求之一。 DAC的每个电流源接收输入电压，其使能或禁止当前源提供或不提供电流。 通过第一触发器（42）或第二触发器（43）将采样的输入电压交替地提供给可切换电流源（41）。 一个触发器对输入电压进行采样，而另一个触发器提供用于启用和禁用可切换电流源（41）的先前采样输入电压。 在输出电压改变到耦合到电流源（53）的晶体管（51）之后的预定时间内，开关（46,47）耦合第一或第二触发器（42,43）的输出电压。
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公开(公告)号：US5525920A
公开(公告)日：1996-06-11
申请号：US431965
申请日：1995-05-01
CPC分类号： H03K5/2472
摘要： Comparator circuit (72) samples a differential input signal at switched capacitor circuit (100). The input signal is stored across capacitors (128, 130, 132, 134). Reference voltages are subtracted from the input signal to produce a difference signal. The difference is compared to a mid-supply reference VMID, and an amplified representation of the signal is produced at the output of differential gain stage (136). Latching output stage (138) uses feedback circuits (204, 211 and 202, 208) to process the amplified signal and to produce a rail to rail representation of the amplified signal at the inputs (146, 148) of SR latch (140). The feedback circuit also powers-down the output stage after processing the amplified signal. Buffer circuits (205, 213 and 214, 212) allow a new signal to be processed by capacitor circuit (100) while the previous signal is being stored in the SR latch.
摘要翻译： 比较器电路（72）在开关电容器电路（100）处采样差分输入信号。 输入信号存储在电容器（128,130,132,134）之间。 从输入信号中减去参考电压以产生差分信号。 将差值与中间电源参考VMID进行比较，并且在差分增益级（136）的输出处产生信号的放大表示。 锁存输出级（138）使用反馈电路（204,211和202,208）来处理放大的信号并且在SR锁存器（140）的输入端（146,148）处产生放大信号的轨至轨表示。 反馈电路在处理放大信号之后还对输出级进行掉电。 当先前的信号被存储在SR锁存器中时，缓冲电路（205,213和214,212）允许由电容器电路（100）处理新的信号。
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公开(公告)号：US20120252396A1
公开(公告)日：2012-10-04
申请号：US13078502
申请日：2011-04-01
申请人： Haolu Xie , Manish N. Shah , Patrick L. Rakers
发明人： Haolu Xie , Manish N. Shah , Patrick L. Rakers
CPC分类号： H04B1/28 , H03D2200/0074 , H03D2200/0088 , H03K2217/0054
摘要： A technique for improving the linearity of a mixer is disclosed. A converter may include a mixer comprising a first metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a first conducting terminal coupled to an input of the converter, and a second conducting terminal coupled to an output of the converter, and a mixer driver having a first output coupled to the gate of the first MOSFET, the mixer driver configured to receive a local-oscillator signal having a first phase and a second phase, drive the first MOSFET off during the first phase of the local-oscillator signal, drive the first MOSFET on for a first period of time in response to a transition from the first phase of the local-oscillator signal to the second phase of the local-oscillator signal, and force the gate of the first MOSFET into a high impedance state for a second period of time during the second phase of the local-oscillator signal and after the expiration of the first period of time.
摘要翻译： 公开了一种改善混频器线性度的技术。 A转换器可以包括混合器，其包括具有栅极的第一金属氧化物半导体场效应晶体管（MOSFET），耦合到转换器的输入端的第一导电端子和耦合到转换器的输出端的第二导通端子，以及 混频器驱动器，其具有耦合到第一MOSFET的栅极的第一输出，混频器驱动器被配置为接收具有第一相位和第二相位的本地振荡器信号，在本机振荡器的第一阶段期间驱动第一MOSFET关断 信号，响应于从本地振荡器信号的第一相到本地振荡器信号的第二相的转变，驱动第一MOSFET导通第一时间段，并迫使第一MOSFET的栅极变为高电平 在本地振荡器信号的第二阶段期间和在第一时间段到期之后的第二时间段的阻抗状态。
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公开(公告)号：US07706765B2
公开(公告)日：2010-04-27
申请号：US09981476
申请日：2001-10-17
申请人： Timothy James Collins , Richard Stanley Rachwalski , Patrick L. Rakers , David P. Gurney , Stephen L. Kuffner
发明人： Timothy James Collins , Richard Stanley Rachwalski , Patrick L. Rakers , David P. Gurney , Stephen L. Kuffner
IPC分类号： H04L12/413 , H04L12/407
CPC分类号： H04L12/413
摘要： A source device (110) receives a carrier signal and continuously monitors the carrier signal for a first predetermined condition and a second predetermined condition. The source device (110) transmits data if the first predetermined condition is satisfied. The source device (110) ceases transmission of data if the first predetermined condition subsequently is not satisfied or if a second predetermined condition is satisfied.
摘要翻译： 源设备（110）接收载波信号并连续地监视载波信号的第一预定条件和第二预定条件。 如果满足第一预定条件，则源装置（110）发送数据。 如果第一预定条件不满足或满足第二预定条件，则源设备（110）停止数据传输。
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公开(公告)号：US07653678B2
公开(公告)日：2010-01-26
申请号：US11457380
申请日：2006-07-13
IPC分类号： G06G7/16
CPC分类号： G06G7/26
摘要： A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.
摘要翻译： 直接数字合成电路（108）包括多个电流源（210,211,212），输出电路（200）和逻辑乘法器电路（202）。 输出电路（200）提供输出的合成波形（164），并包括第一分支（206）和第二分支（208）。 逻辑乘法器电路（202）可操作地耦合到多个电流源（210,211,212）和输出电路（200）。 逻辑乘法器电路（202）可操作以接收多个信号。 逻辑乘法器电路还可操作以选择性地将通过第一分支（206）的第一电流流过确定的幅度，并且基于多个信号减少通过第二分支（208）的确定的幅度的第二电流。 合成波形（164）基于第一和第二电流。
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10.发明授权Method and apparatus for data backup and restoration in a portable data device 有权在便携式数据设备中进行数据备份和恢复的方法和装置公开(公告)号：US06317755B1
公开(公告)日：2001-11-13
申请号：US09360571
申请日：1999-07-26
IPC分类号： G06F1730
CPC分类号： G07F7/1008 , G06F11/1441 , G06Q20/341 , G06Q20/3576 , Y10S707/99955
摘要： A portable data device (300) having a memory (302) is provided. The memory (302) is segmented into a plurality of sectors (304-312). A backup memory buffer (312) and a plurality of applications (304-310) are programmed into the plurality of sectors, wherein the backup memory buffer (312) is jointly used by the plurality of applications (304-310). A valid state of data is stored in the backup memory buffer (312) prior to performing a transaction for a first application (304). The valid state of data is restored in the first application (304) upon power up of the portable data device (300) in an event the transaction is terminated prior to completion, wherein the step of restoring is independent of a next application in which a next transaction is performed.
摘要翻译： 提供具有存储器（302）的便携式数据设备（300）。 存储器（302）被分割成多个扇区（304-312）。 备份存储器缓冲器（312）和多个应用程序（304-310）被编程到多个扇区中，其中备用存储器缓冲器（312）由多个应用程序共同使用（304-310）。 在对第一应用执行交易之前，将有效的数据状态存储在备份存储器缓冲器（312）中（304）。 在事务在完成之前被终止的情况下，在便携式数据设备（300）上电时，在第一应用（304）中恢复数据的有效状态，其中恢复步骤独立于下一个应用 执行下一个事务。
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