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1.发明申请MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation 有权MOS晶体管和用SiON蚀刻停止层形成MOS晶体管的方法，其保护晶体管不受PID和热载流子劣化公开(公告)号：US20090146192A1
公开(公告)日：2009-06-11
申请号：US12001370
申请日：2007-12-10
申请人： Douglas Brisbin , Prasad Chaparala , Denis Finbarr O'Connell , Heather McCulloh , Sergei Drizlikh
发明人： Douglas Brisbin , Prasad Chaparala , Denis Finbarr O'Connell , Heather McCulloh , Sergei Drizlikh
IPC分类号： H01L29/78 , H01L21/311
CPC分类号： H01L21/3145 , H01L21/31116 , H01L29/665 , H01L29/78
摘要： A MOS transistor is formed with a dual-layer silicon oxynitride (SiON) etch stop film that protects the transistor from plasma induced damage (PID) and hot carrier degradation, thereby improving the reliability of the transistors. The first SiON layer is formed with SiH4 at a first flow rate, and the second SiON layer is formed with SiH4 at a second higher flow rate.
摘要翻译： MOS晶体管形成有双层氮氧化硅（SiON）蚀刻停止膜，其保护晶体管免受等离子体引起的损伤（PID）和热载流子劣化，从而提高晶体管的可靠性。 第一SiON层以第一流速由SiH 4形成，并且第二SiON层以第二较高流速形成SiH4。
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2.发明授权MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation 有权MOS晶体管和用SiON蚀刻停止层形成MOS晶体管的方法，其保护晶体管不受PID和热载流子劣化公开(公告)号：US07645657B2
公开(公告)日：2010-01-12
申请号：US12001370
申请日：2007-12-10
申请人： Douglas Brisbin , Prasad Chaparala , Denis Finbarr O'Connell , Heather McCulloh , Sergei Drizlikh
发明人： Douglas Brisbin , Prasad Chaparala , Denis Finbarr O'Connell , Heather McCulloh , Sergei Drizlikh
IPC分类号： H01L21/336
CPC分类号： H01L21/3145 , H01L21/31116 , H01L29/665 , H01L29/78
摘要： A MOS transistor is formed with a dual-layer silicon oxynitride (SiON) etch stop film that protects the transistor from plasma induced damage (PID) and hot carrier degradation, thereby improving the reliability of the transistors. The first SiON layer is formed with SiH4 at a first flow rate, and the second SiON layer is formed with SiH4 at a second higher flow rate.
摘要翻译： MOS晶体管形成有双层氮氧化硅（SiON）蚀刻停止膜，其保护晶体管免受等离子体引起的损伤（PID）和热载流子劣化，从而提高晶体管的可靠性。 第一SiON层以第一流速由SiH 4形成，并且第二SiON层以第二较高流速形成SiH4。
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3.发明授权Method and apparatus for reducing plasma process induced damage in integrated circuits 有权用于减少集成电路中等离子体工艺引起的损坏的方法和装置公开(公告)号：US08471369B1
公开(公告)日：2013-06-25
申请号：US10912660
申请日：2004-08-05
IPC分类号： H01L23/58
CPC分类号： H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An insulating material interposed between two conductive materials can experience plasma process induced damage (PPID) when a plasma process is used to deposit a dielectric onto one of the conductive materials. This PPID can be reduced by reducing electric charge accumulation on the one conductive material during the plasma process dielectric deposition.
摘要翻译： 插入在两个导电材料之间的绝缘材料在使用等离子体工艺将电介质沉积到导电材料之一上时可能经历等离子体工艺引起的损伤（PPID）。 通过在等离子体处理介电沉积期间减少一种导电材料上的电荷积累，可以减少该PPID。
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公开(公告)号：US06927474B1
公开(公告)日：2005-08-09
申请号：US10428992
申请日：2003-05-01
IPC分类号： G11C17/16 , H01L23/525 , H01L29/00
CPC分类号： G11C17/16 , H01L23/5252 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-to-metal capacitor in a semiconductor integrated circuit is converted to a conductive structure by connecting the first metal plate of the capacitor to ground and the second metal plate of the capacitor to a programming voltage, thus causing the insulator material to breakdown and conduct current from the first plate to the second plate.
摘要翻译： 半导体集成电路中的金属对金属电容器通过将电容器的第一金属板接地和电容器的第二金属板连接到编程电压而被转换为导电结构，从而导致绝缘体材料破坏， 将电流从第一板传导到第二板。
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5.发明申请METHOD OF SELECTIVE OXYGEN IMPLANTATION TO DIELECTRICALLLY ISOLATE SEMICONDUCTOR DEVICES USING NO EXTRA MASKS 审中-公开使用无外延掩模进行电介质分离半导体器件的选择性氧化方法公开(公告)号：US20100190316A1
公开(公告)日：2010-07-29
申请号：US12753636
申请日：2010-04-02
IPC分类号： H01L21/762
CPC分类号： H01L27/0921 , H01L21/76267 , H01L21/823878 , H01L21/84
摘要： A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk silicon that is latch-up immune.
摘要翻译： 制造集成电路结构的方法利用选择性氧注入来使用无额外掩模来介电地隔离半导体结构。 利用现有掩模将氧气引入体硅中，随后进行热氧化物生长。 由于该方法使用体硅，所以它比绝缘体上硅（SOI）技术便宜。 这也导致大量的硅是闩锁免疫。
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6.发明授权Method of selective oxygen implantation to dielectrically isolate semiconductor devices using no extra masks 有权选择性氧注入方法，使用无额外掩模来介电隔离半导体器件公开(公告)号：US07741190B2
公开(公告)日：2010-06-22
申请号：US11891170
申请日：2007-08-09
IPC分类号： H01L21/76
CPC分类号： H01L27/0921 , H01L21/76267 , H01L21/823878 , H01L21/84
摘要： A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk-silicon that is latch-up immune.
摘要翻译： 制造集成电路结构的方法利用选择性氧注入来使用无额外掩模来介电地隔离半导体结构。 利用现有掩模将氧气引入体硅中，随后进行热氧化物生长。 由于该方法使用体硅，所以它比绝缘体上硅（SOI）技术便宜。 它也导致大块硅，这是闩锁免疫。
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7.发明申请Method of selective oxygen implantation to dielectrically isolate semiconductor devices using no extra masks 有权选择性氧注入方法，使用无额外掩模来介电隔离半导体器件公开(公告)号：US20090042357A1
公开(公告)日：2009-02-12
申请号：US11891170
申请日：2007-08-09
IPC分类号： H01L21/76
CPC分类号： H01L27/0921 , H01L21/76267 , H01L21/823878 , H01L21/84
摘要： A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk-silicon that is latch-up immune.
摘要翻译： 制造集成电路结构的方法利用选择性氧注入来使用无额外掩模来介电地隔离半导体结构。 利用现有掩模将氧气引入体硅中，随后进行热氧化物生长。 由于该方法使用体硅，所以它比绝缘体上硅（SOI）技术便宜。 它也导致大块硅，这是闩锁免疫。
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