公开(公告)号：US4156796A

公开(公告)日：1979-05-29

申请号：US855578

申请日：1977-11-29

申请人： Douglas M. O'Neal ,  Donald V. Wildes

发明人： Douglas M. O'Neal ,  Donald V. Wildes

IPC分类号： H04L29/04 ,  G06F13/00 ,  G06F13/12 ,  G06F13/40 ,  H04Q3/54 ,  G06F9/16

CPC分类号： G06F13/124 ,  G06F13/4022

摘要： A micro processor controlled user programmable communications multiplexer subsystem (herein referred to by the symbol PCS) capable of transmitting and receiving data on any one or more of 32 communications lines simultaneously. Each line may be dynamically assigned to a variety of communication characteristics, such as line speeds, character lengths, synchronous, or asynchronous operation, and code structures as well as protocol selections.The system of the invention provides the capability for the user to write his communications programs using novel operations commands that provide code structure and protocol independence as well as communication line independence. Various hardware features and queuing techniques are employed in order to maintain high transmission rates.Variable line scanning in the Teleprocessing Time Division Multiplexer of the PCS is programmably permissible; i.e., the time base for line scanning is fixed and is a multiple of the communication line rate, although the actual line to be scanned is programmably variable. The program ability is provided by a continuously scanned storage array which contains physical line addresses of the time division multiplexer. The scanning mechanism, while running, prioritizes the transmit buffer servicing of the individual lines.

摘要翻译： 一种微处理器控制的用户可编程通信多路复用器子系统（这里称为符号PCS），能够同时在32个通信线路中的任何一个或多个通信线路上发送和接收数据。 每行可以动态分配给各种通信特性，例如线路速度，字符长度，同步或异步操作，以及代码结构以及协议选择。

公开(公告)号：USD362250S

公开(公告)日：1995-09-12

申请号：US24719

申请日：1994-06-20

申请人： James A. Harding ,  Victor S. Moore ,  Douglas M. O'Neal

设计人： James A. Harding ,  Victor S. Moore ,  Douglas M. O'Neal

公开(公告)号：US4514823A

公开(公告)日：1985-04-30

申请号：US339525

申请日：1982-01-15

申请人： Richard N. Mendelson ,  Douglas M. O'Neal ,  Leo A. Sharp, Jr.

发明人： Richard N. Mendelson ,  Douglas M. O'Neal ,  Leo A. Sharp, Jr.

IPC分类号： G06F13/38 ,  G06F13/12 ,  G06F13/28 ,  G06F9/00

CPC分类号： G06F13/282 ,  G06F13/122

摘要： There is disclosed apparatus and a method for extending a parallel channel of the host processor over a serial link to a remote peripheral device. The apparatus includes a microprocessor within I/O channel extension logic which responds to either instructions or data from a host processor. The instructions are of the type commanding the I/O device to perform a specific operation and the data is provided in response to requests for data from the I/O device. The channel extension logic is coupled to the host processor's channel and thus is able to obtain data from the host storage by cycle steal techniques. Within the channel extension logic are means to serialize the information and transmit it in a serial manner over the link. The microprocessor within the channel extension logic creates a frame, including a control byte, which identifies the type of information followed by the data, which frame is then communicated over the serial link to the I/O device. The I/O device also includes a microprocessor and associated logic which responds to the frames communicated by the channel extension logic and generates a frame consisting of a control byte identifying the information type and associated data which is then communicated back over the serial link to the channel extension logic to request action by the channel extension logic or indicate completion of the operation. The I/O device may, for instance, request data be obtained from or stored in the host memory by cycle steal techniques and thereby utilize the features of the host and host channel despite only being coupled thereto by a serial link.

摘要翻译： 公开了通过串行链路将主处理器的并行通道扩展到远程外围设备的装置和方法。 该装置包括在I / O通道扩展逻辑中的微处理器，其响应来自主机处理器的指令或数据。 指令是指令I / O设备执行特定操作的类型，并且响应于来自I / O设备的数据请求而提供数据。 信道扩展逻辑耦合到主处理器的信道，因此能够通过循环窃取技术从主机存储获得数据。 在信道扩展逻辑中是用于串行化信息并通过链路以串行方式发送信息的手段。 信道扩展逻辑内的微处理器创建一个帧，包括一个控制字节，该控制字节标识随后数据的信息类型，然后通过串行链路将该帧传送到I / O设备。 I / O设备还包括微处理器和相关联的逻辑，其响应由信道扩展逻辑传送的帧，并产生由标识信息类型和相关联的数据的控制字节组成的帧，然后通过串行链路将其传送回到 信道扩展逻辑，以通过信道扩展逻辑请求动作或指示操作的完成。 例如，I / O设备可以通过循环窃取技术从主机存储器中获取或存储数据，从而利用主机和主机信道的特征，尽管仅通过串行链路耦合到主机和主机信道。