公开(公告)号：US20110012176A1

公开(公告)日：2011-01-20

申请号：US12505580

申请日：2009-07-20

申请人： Dureseti CHIDAMBARRAO ,  Xiao Hu LIU ,  Lidija SEKARIC

发明人： Dureseti CHIDAMBARRAO ,  Xiao Hu LIU ,  Lidija SEKARIC

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7842 ,  H01L29/7845

摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

摘要翻译： 电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。 此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加 取决于通道长度相对于晶体结构的对准。 给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。

公开(公告)号：US20120322215A1

公开(公告)日：2012-12-20

申请号：US13593686

申请日：2012-08-24

申请人： Dureseti CHIDAMBARRAO ,  Xiao Hu LIU ,  Lidija SEKARIC

发明人： Dureseti CHIDAMBARRAO ,  Xiao Hu LIU ,  Lidija SEKARIC

IPC分类号： H01L21/8238 ,  B82Y40/00

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7842 ,  H01L29/7845

摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

摘要翻译： 电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。 此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加 取决于通道长度相对于晶体结构的对准。 给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。

公开(公告)号：US20070296038A1

公开(公告)日：2007-12-27

申请号：US11848268

申请日：2007-08-31

申请人： Huajie CHEN ,  Dureseti CHIDAMBARRAO ,  Omer DOKUMACI

发明人： Huajie CHEN ,  Dureseti CHIDAMBARRAO ,  Omer DOKUMACI

IPC分类号： H01L27/01

CPC分类号： H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

公开(公告)号：US20080179680A1

公开(公告)日：2008-07-31

申请号：US12054812

申请日：2008-03-25

申请人： Dureseti CHIDAMBARRAO ,  Anda C. Mocuta ,  Dan M. Mocuta ,  Carl Radens

发明人： Dureseti CHIDAMBARRAO ,  Anda C. Mocuta ,  Dan M. Mocuta ,  Carl Radens

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

摘要翻译： 本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。 在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。 此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

公开(公告)号：US20070264783A1

公开(公告)日：2007-11-15

申请号：US11782429

申请日：2007-07-24

申请人： Huajie CHEN ,  Dureseti CHIDAMBARRAO ,  Omer DOKUMACI

发明人： Huajie CHEN ,  Dureseti CHIDAMBARRAO ,  Omer DOKUMACI

IPC分类号： H01L21/8234

CPC分类号： H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

摘要翻译： 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

公开(公告)号：US20070231979A1

公开(公告)日：2007-10-04

申请号：US11757883

申请日：2007-06-04

申请人： Dureseti CHIDAMBARRAO ,  Omer DOKUMACI ,  Oleg GLUSCHENKOV

发明人： Dureseti CHIDAMBARRAO ,  Omer DOKUMACI ,  Oleg GLUSCHENKOV

IPC分类号： H01L21/762

CPC分类号： H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。