Piezo-effect transistor device and applications
    3.
    发明授权
    Piezo-effect transistor device and applications 有权
    压电效应晶体管器件及应用

    公开(公告)号:US08159854B2

    公开(公告)日:2012-04-17

    申请号:US12495027

    申请日:2009-06-30

    IPC分类号: G11C5/06

    摘要: A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode and a third electrode, wherein the first electrode comprises a gate terminal, the second electrode comprises a common terminal, and the third electrode comprises an output terminal such that an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material.

    摘要翻译: 压电效应晶体管(PET)器件包括设置在第一和第二电极之间的压电(PE)材料; 以及设置在第二电极和第三电极之间的压阻(PR)材料,其中第一电极包括栅极端子,第二电极包括公共端子,并且第三电极包括输出端子,使得PR的电阻 材料取决于PE材料上施加的电压,通过PE材料对PR材料的施加压力。

    CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME
    7.
    发明申请
    CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME 有权
    CRACKSTOP结构及其制造方法

    公开(公告)号:US20100013043A1

    公开(公告)日:2010-01-21

    申请号:US12174994

    申请日:2008-07-17

    IPC分类号: H01L29/00 H01L21/00

    摘要: An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate.

    摘要翻译: 集成电路芯片和制造集成电路芯片的方法。 集成电路芯片包括:接近集成电路芯片的周边的连续的第一应力环,第一应力环的相应边缘平行于集成电路芯片的相应边缘; 所述第一应力环与所述集成电路芯片的周边之间的连续的第二应力环,所述第二应力环平行于所述集成电路芯片的相应边缘的相应边缘,所述第一和第二应力环具有相反的内应力; 第一应力环和第二应力环之间的连续间隙; 以及从基板上的第一布线电平到最后布线电平的一组布线电平。

    Enhanced Transistor Performance by Non-Conformal Stressed Layers
    9.
    发明申请
    Enhanced Transistor Performance by Non-Conformal Stressed Layers 有权
    通过非保形强制层增强晶体管性能

    公开(公告)号:US20080217663A1

    公开(公告)日:2008-09-11

    申请号:US11682554

    申请日:2007-03-06

    IPC分类号: H01L27/098 H01L21/8238

    CPC分类号: H01L21/823807 H01L29/7843

    摘要: NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto the channel of the device, in comparison to stressing layers which are conformal. The method for overlaying in a non-conformal manner includes non-conformal deposition techniques, as well as, conformal depositions where subsequently the layer is turned into a non-conformal one by etching.

    摘要翻译: 公开了具有单独应变通道区域的NFET和PFET器件及其制造方法。 应力层以使得应力层相对于浇口不共面的方式覆盖该装置。 与应力层相比,应力层的非共形性增加了施加到器件的通道上的应力的量。 以非共形方式覆盖的方法包括非共形沉积技术以及保形沉积,其中随后通过蚀刻将该层转变为非共形沉积技术。

    Heat-shielded low power PCM-based reprogrammable EFUSE device
    10.
    发明授权
    Heat-shielded low power PCM-based reprogrammable EFUSE device 有权
    隔热低功耗基于PCM的可编程EFUSE设备

    公开(公告)号:US07394089B2

    公开(公告)日:2008-07-01

    申请号:US11467294

    申请日:2006-08-25

    IPC分类号: H01L47/00

    摘要: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

    摘要翻译: 用于集成电路器件的电可重新编程保险丝(eFUSE)器件包括细长的加热器元件,围绕细长加热器元件的外表面的电绝缘衬垫,其对应于其纵向轴线,留下细长加热器的相对端 元件与第一和第二加热器电极电接触。 相变材料(PCM)围绕电绝缘衬垫的外表面的一部分,热和电绝缘层围绕PCM的外表面,其中第一和第二熔丝电极与PCM的相对端电接触。 PCM被封装在电绝缘衬垫,热和电绝缘层以及第一和第二熔丝电极中。