公开(公告)号：US20230168936A1

公开(公告)日：2023-06-01

申请号：US17980008

申请日：2022-11-03

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jaehoon CHUNG ,  Young-Su KWON ,  Jin Ho HAN

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: A method and apparatus for allocating tasks through relocating kernel data based on a size of systolic array included in each of the plurality of processors, and relocating input feature map (IFM) data based on a number of the plurality of processors are provided.

公开(公告)号：US20220147485A1

公开(公告)日：2022-05-12

申请号：US17525146

申请日：2021-11-12

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jaehoon CHUNG

IPC: G06F15/80 ,  G06F9/30 ,  G06F1/10

Abstract: Disclosed is an electronic device which includes a main processor, and a systolic array processor, and the systolic array processor includes processing elements, a kernel data memory that provides a kernel data set to the processing elements, a data memory that provides an input data set to the processing elements, and a controller that provides commands to the processing elements. The main processor translates source codes associated with the systolic array processor into commands of the systolic array processor, calculates a switching activity value based on the commands, and stores the translated commands and the switching activity value to a machine learning module, which is based on the systolic array processor.

公开(公告)号：US20200175355A1

公开(公告)日：2020-06-04

申请号：US16677835

申请日：2019-11-08

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jaehoon CHUNG ,  Young-Su KWON ,  Chun-Gi LYUH ,  Chan KIM ,  Hyun Mi KIM ,  Jeongmin YANG ,  Yong Cheol Peter CHO

IPC: G06N3/063 ,  G06N3/04 ,  G06F15/80

Abstract: A neural network accelerator in which processing elements are configured in a systolic array structure includes a memory to store a plurality of feature data including first and second feature data and a plurality of kernel data including first and second kernel data, a first processing element to perform an operation based on the first feature data and the first kernel data and output the first feature data, a selection circuit to select one of the first feature data and the second feature data, based on a control signal, and output the selected feature data, a second processing element to perform an operation based on the selected feature data and one of the first and the second kernel data, and a controller to generate the control signal, based on a neural network characteristic associated with the plurality of feature data and kernel data.

公开(公告)号：US20190079801A1

公开(公告)日：2019-03-14

申请号：US16038243

申请日：2018-07-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Chun-Gi LYUH ,  Young-Su KWON ,  Chan KIM ,  Hyun Mi KIM ,  Jeongmin YANG ,  Jaehoon CHUNG ,  Yong Cheol Peter CHO

IPC: G06F9/50 ,  G06N3/063 ,  G06F9/30 ,  G06F9/38 ,  G06N5/04

Abstract: Provided is a neural network accelerator which performs a calculation of a neural network provided with layers, the neural network accelerator including a kernel memory configured to store kernel data related to a filter, a feature map memory configured to store feature map data which are outputs of the layers, and a Processing Element (PE) array including PEs arranged along first and second directions, wherein each of the PEs performs a calculation using the feature map data transmitted in the first direction from the feature map memory and the kernel data transmitted in the second direction from the kernel memory, and transmits a calculation result to the feature map memory in a third direction opposite to the first direction.

公开(公告)号：US20190164037A1

公开(公告)日：2019-05-30

申请号：US16204599

申请日：2018-11-29

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Chan KIM ,  Young-Su KWON ,  Hyun Mi KIM ,  Chun-Gi LYUH ,  Yong Cheol Peter CHO ,  Min-Seok CHOI ,  Jeongmin YANG ,  Jaehoon CHUNG

IPC: G06N3/04 ,  G06N3/08 ,  G06F15/80 ,  G06F17/15

Abstract: In the present invention, by providing an apparatus for processing a convolutional neural network (CNN), including a weight memory configured to store a first weight group of a first layer, a feature map memory configured to store an input feature map where the first weight group is to be applied, an address generator configured to determine a second position spaced from a first position of a first input pixel of the input feature map based on a size of the first weight group, and determine a plurality of adjacent pixels adjacent to the second position; and a processor configured to apply the first weight group to the plurality of adjacent pixels to obtain a first output pixel corresponding to the first position, a memory space may be efficiently used by saving the memory space.

公开(公告)号：US20190164035A1

公开(公告)日：2019-05-30

申请号：US16201871

申请日：2018-11-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-Su KWON ,  Chan KIM ,  Hyun Mi KIM ,  Jeongmin YANG ,  Chun-Gi LYUH ,  Jaehoon CHUNG ,  Yong Cheol Peter CHO

IPC: G06N3/04

Abstract: A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.