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1.发明申请公开(公告)号：US20190164037A1
公开(公告)日：2019-05-30
申请号：US16204599
申请日：2018-11-29
Inventor： Chan KIM , Young-Su KWON , Hyun Mi KIM , Chun-Gi LYUH , Yong Cheol Peter CHO , Min-Seok CHOI , Jeongmin YANG , Jaehoon CHUNG
Abstract: In the present invention, by providing an apparatus for processing a convolutional neural network (CNN), including a weight memory configured to store a first weight group of a first layer, a feature map memory configured to store an input feature map where the first weight group is to be applied, an address generator configured to determine a second position spaced from a first position of a first input pixel of the input feature map based on a size of the first weight group, and determine a plurality of adjacent pixels adjacent to the second position; and a processor configured to apply the first weight group to the plurality of adjacent pixels to obtain a first output pixel corresponding to the first position, a memory space may be efficiently used by saving the memory space.
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2.发明申请公开(公告)号：US20200175293A1
公开(公告)日：2020-06-04
申请号：US16694899
申请日：2019-11-25
Inventor： Jin Ho HAN , Young-Su KWON , Yong Cheol Peter CHO , Min-Seok CHOI
Abstract: Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores arranged in rows and columns and configured to perform a pattern recognition operation on an input feature using a kernel coefficient in response to each instruction, an instruction memory configured to provide the instruction to each of the plurality of nano cores, a feature memory configured to provide the input feature to each of the plurality of nano cores, a kernel memory configured to provide the kernel coefficients to the plurality of nano cores, and a functional safety processor core configured to receive a result of a pattern recognition operation outputted from the plurality of nano cores to detect the presence of a recognition error, and perform a fault tolerance function on the detected recognition error.
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Patent Agency Ranking
公开(公告)号：US20190114236A1
公开(公告)日：2019-04-18
申请号：US16022334
申请日：2018-06-28
Inventor： Jin Ho HAN , Min-Seok CHOI , Young-Su KWON
Abstract: A network on-chip may include a master circuit that outputs write data or receives read data, a slave circuit that stores the write data or outputs the read data, a master network interface circuit that generates a first error correction code associated with the write data, a slave network interface circuit that generates a second error correction code associated with the read data, and an on-chip network circuit that transmits the write data and the first error correction code to the slave network interface circuit or transmits the read data and the second error correction code to the master network interface circuit, the master network interface circuit decodes the read data and the second error correction code and requests the read data again or generates a first fault signal, and the slave network interface circuit decodes the write data and the first error correction code and requests the write data again or generates a second fault signal.
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公开(公告)号：US20220164308A1
公开(公告)日：2022-05-26
申请号：US17523615
申请日：2021-11-10
Inventor： Chun-Gi LYUH , Min-Seok CHOI , Young-Su KWON , Jin Ho HAN
Abstract: Disclosed is a processor according to the present disclosure, which includes processing elements, a kernel data memory that provides a kernel data set to the processing elements, a data memory that provides an input data set to the processing elements, and a controller that provides commands to the processing elements, and a first processing element among the processing elements delays a first command received from the controller and first input data received from the data memory for a delay time, and then transfers the delayed first command and the delayed first input data to a second processing element, and the controller adjusts the delay time.
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公开(公告)号：US20210182222A1
公开(公告)日：2021-06-17
申请号：US17119387
申请日：2020-12-11
Inventor： Jin Ho HAN , Min-Seok CHOI , Young-Su KWON
IPC: G06F13/16 , G06F13/28 , G06F12/1081 , G06F12/02
Abstract: Disclosed is a cache including a dataflow controller for transmitting first data to a first processor and receiving second data from the first processor, an external direct memory access (DMA) controller for receiving the first data from an external memory to transmit the first data to the dataflow controller and receiving the second data from the dataflow controller to transmit the second data to the external memory, a scratchpad memory for storing the first data or the second data transmitted between the dataflow controller and the external DMA controller, a compression/decompression device for compressing data to be transmitted from the scratchpad memory to the external memory and decompressing data transmitted from the external memory to the scratchpad memory, and a transfer state buffer for storing transfer state information associated with data transfer between the dataflow controller and the external DMA controller.
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公开(公告)号：US20200167245A1
公开(公告)日：2020-05-28
申请号：US16694913
申请日：2019-11-25
Inventor： Jin Ho HAN , Young-Su KWON , Min-Seok CHOI
Abstract: Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.
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公开(公告)号：US20190108105A1
公开(公告)日：2019-04-11
申请号：US16117403
申请日：2018-08-30
Inventor： Jin Ho HAN , Min-Seok CHOI , Young-Su KWON
IPC: G06F11/14
Abstract: Provided is a semiconductor system including: a fault detector configured to obtain fault information related to a fault occurring in a first intellectual property (IP); a fault manager configured to store recovery information providing one or more recovery methods related to the fault information and determine a recovery method for recovering the fault occurring in the first IP among the one or more recovery methods based on the recovery information; and a fault recovery module configured to control the first IP based on the determined recovery method. The determined recovery method involves communication between the first IP and a second IP and the fault occurring in the first IP is recovered based on data delivered according to the communication between the first IP and the second IP.
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