NEURAL NETWORK ACCELERATOR WITH SYSTOLIC ARRAY STRUCTURE

    公开(公告)号:US20200175355A1

    公开(公告)日:2020-06-04

    申请号:US16677835

    申请日:2019-11-08

    Abstract: A neural network accelerator in which processing elements are configured in a systolic array structure includes a memory to store a plurality of feature data including first and second feature data and a plurality of kernel data including first and second kernel data, a first processing element to perform an operation based on the first feature data and the first kernel data and output the first feature data, a selection circuit to select one of the first feature data and the second feature data, based on a control signal, and output the selected feature data, a second processing element to perform an operation based on the selected feature data and one of the first and the second kernel data, and a controller to generate the control signal, based on a neural network characteristic associated with the plurality of feature data and kernel data.

    CAN CONTROLLER AND DATA TRANSMISSION METHOD USING THE SAME

    公开(公告)号:US20180159699A1

    公开(公告)日:2018-06-07

    申请号:US15823104

    申请日:2017-11-27

    Abstract: Provided are Controller Area Network (CAN) controller and a data transmission method using the same. The CAN controller includes a receiver, a reception First in First out (FIFO) memory, a transmission FIFO memory, and a transmitter. The receiver is configured to analyze reception information received from a CAN bus according to a set protocol. The reception FIFO memory is configured to store the reception information to be overwritten on previously stored reception information based on identification data of the reception information and a bus load. The transmission FIFO memory is configured to store the transmission information to be overwritten on previously stored transmission information based on identification data of the transmission information and a processor load of the processor. The transmitter is configured to set the protocol and transmit the transmission information stored in the transmission FIFO memory to the CAN bus.

    NEURAL NETWORK COMPUTING DEVICE AND OPERATION METHOD THEREOF

    公开(公告)号:US20190220739A1

    公开(公告)日:2019-07-18

    申请号:US16225729

    申请日:2018-12-19

    CPC classification number: G06N3/08 G06F7/523

    Abstract: Provided is a neural network computing device including a neural network memory configured to store input data, a kernel memory configured to store kernel data corresponding to the input data, a kernel data controller configured to determine whether or not a first part of the kernel data matches a predetermined bit string, and if the first part matches the predetermined bit string, configured to generate a plurality of specific data based on a second part of the kernel data, and a neural core configured to perform a first operation between one of the plurality of specific data and the input data.

    GENERAL-PURPOSE COMPUTING ACCELERATOR AND OPERATION METHOD THEREOF

    公开(公告)号:US20220147353A1

    公开(公告)日:2022-05-12

    申请号:US17446678

    申请日:2021-09-01

    Inventor: Jeongmin YANG

    Abstract: Disclosed is a general-purpose computing accelerator which includes a memory including an instruction cache, a first executing unit performing a first computation operation, a second executing unit performing a second computation operation, an instruction fetching unit fetching an instruction stored in the instruction cache, a decoding unit that decodes the instruction, and a state control unit controlling a path of the instruction depending on an operation state of the second executing unit. The decoding unit provides the instruction to the first executing unit when the instruction is of a first type and provides the instruction to the state control unit when the instruction is of a second type. Depending on the operation state of the second executing unit, the state control unit provides the instruction of the second type to the second executing unit or stores the instruction of the second type as a register file in the memory.

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