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    NEURAL NETWORK ACCELERATOR WITH SYSTOLIC ARRAY STRUCTURE
    1.
    发明申请
    NEURAL NETWORK ACCELERATOR WITH SYSTOLIC ARRAY STRUCTURE 审中-公开

    公开(公告)号：US20200175355A1

    公开(公告)日：2020-06-04

    申请号：US16677835

    申请日：2019-11-08

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Jaehoon CHUNG ,  Young-Su KWON ,  Chun-Gi LYUH ,  Chan KIM ,  Hyun Mi KIM ,  Jeongmin YANG ,  Yong Cheol Peter CHO

    IPC: G06N3/063 ,  G06N3/04 ,  G06F15/80

    Abstract: A neural network accelerator in which processing elements are configured in a systolic array structure includes a memory to store a plurality of feature data including first and second feature data and a plurality of kernel data including first and second kernel data, a first processing element to perform an operation based on the first feature data and the first kernel data and output the first feature data, a selection circuit to select one of the first feature data and the second feature data, based on a control signal, and output the selected feature data, a second processing element to perform an operation based on the selected feature data and one of the first and the second kernel data, and a controller to generate the control signal, based on a neural network characteristic associated with the plurality of feature data and kernel data.

    DEVICE FOR REORGANIZABLE NEURAL NETWORK COMPUTING
    3.
    发明申请
    DEVICE FOR REORGANIZABLE NEURAL NETWORK COMPUTING 审中-公开

    公开(公告)号：US20190164035A1

    公开(公告)日：2019-05-30

    申请号：US16201871

    申请日：2018-11-27

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Young-Su KWON ,  Chan KIM ,  Hyun Mi KIM ,  Jeongmin YANG ,  Chun-Gi LYUH ,  Jaehoon CHUNG ,  Yong Cheol Peter CHO

    IPC: G06N3/04

    Abstract: A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.

    METHOD AND APPARATUS FOR CONTROLLING ELECTRONIC DEVICE
    6.
    发明申请
    METHOD AND APPARATUS FOR CONTROLLING ELECTRONIC DEVICE 有权
    用于控制电子设备的方法和装置

    公开(公告)号：US20140223349A1

    公开(公告)日：2014-08-07

    申请号：US14134387

    申请日：2013-12-19

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Hong Chang SHIN ,  Gi Mun UM ,  Chan KIM ,  Hyun LEE ,  Eung Don LEE ,  Won Sik CHEONG ,  Nam Ho HUR

    IPC: G06F3/0484

    CPC classification number: G06F3/0484 ,  G06F17/30879 ,  G06T7/73 ,  G06T19/006

    Abstract: There are provided a method and apparatus for controlling an electronic device. The apparatus for controlling an electronic device includes a marker recognition unit configured to recognize the marker of the electronic device and a control unit configured to perform communication with the electronic device based on the marker and control the electronic device using a Graphic User Interface (GUI) program received from the electronic device.

    Abstract translation: 提供了一种用于控制电子设备的方法和装置。 用于控制电子设备的设备包括：识别电子设备的标记的标识识别单元和配置为基于标记与电子设备进行通信的控制单元，并使用图形用户界面（GUI）控制电子设备， 从电子设备接收的节目。

    NEURAL NETWORK ACCELERATOR CONFIGURED TO PERFORM OPERATION ON LOGARITHM DOMAIN
    7.
    发明申请
    NEURAL NETWORK ACCELERATOR CONFIGURED TO PERFORM OPERATION ON LOGARITHM DOMAIN 有权

    公开(公告)号：US20210334635A1

    公开(公告)日：2021-10-28

    申请号：US17238490

    申请日：2021-04-23

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： In San JEON ,  Chan KIM

    IPC: G06N3/063

    Abstract: Disclosed is a neural network accelerator including a maximum value determiner outputting a maximum value based on a first magnitude component corresponding to first input data and a second magnitude component corresponding to second input data, a sign determiner outputting a sign component corresponding to the maximum value among a first sign component corresponding to the first input data and a second sign component corresponding to the second input data, as an output sign component, an offset operator quantizing a difference between the first magnitude component and the second magnitude component and outputting an output offset based on the first sign component, the second sign component, and the quantization result, and a magnitude operator calculating an output magnitude component of an output data based on the maximum value and the output offset. Each of the first input data and the second input data is data on a logarithm domain.

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