公开(公告)号：US09654119B2

公开(公告)日：2017-05-16

申请号：US15184113

申请日：2016-06-16

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ja Yol Lee ,  Minjae Lee ,  Cheon Soo Kim ,  Jaehyun Kang ,  Minuk Heo

IPC: H03L7/18 ,  H03L7/093 ,  H03L7/085 ,  H03L7/099

CPC classification number: H03L7/093 ,  H03L7/085 ,  H03L7/099 ,  H03L7/18

Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.

公开(公告)号：US09735788B2

公开(公告)日：2017-08-15

申请号：US15185438

申请日：2016-06-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Ja Yol Lee ,  Minjae Lee ,  Cheon Soo Kim ,  Jaehyun Kang ,  Junsoo Ko

IPC: H03L7/18 ,  H03L1/00 ,  H03L7/099 ,  H03L7/093 ,  H03K5/135 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00052 ,  H03L7/081 ,  H03L2207/50

Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.