公开(公告)号：US07207018B2

公开(公告)日：2007-04-17

申请号：US10910624

申请日：2004-08-04

申请人： Vyacheslav L. Zavadsky ,  Elmehdi Aitnouri ,  Edward Keyes ,  Jason Abt ,  Val Gont ,  Stephen Begg

发明人： Vyacheslav L. Zavadsky ,  Elmehdi Aitnouri ,  Edward Keyes ,  Jason Abt ,  Val Gont ,  Stephen Begg

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm. This algorithm determines the areas of high density where high flow is dictated by the triangle or trapezoid having the lowest current capacity. The areas of high density are flagged as points where short circuits may exist. These flagged points may then be investigated to confirm whether they are short circuits.

摘要翻译： 根据本发明的方法和装置确定在集成电路布局的多边形表示中不正确连接的多边形的位置。 这些不正确连接的多边形导致短路，这通常发生在诸如电源和地面之类的主要信号总线上。 确定短路的确切位置可能是耗时的。 本发明包括将包括每个导电层的多边形表示细分为预定形状（例如三角形或梯形）的步骤。 然后，每个三角形或梯形被转换成节点以开发节点，其中节点彼此直接相连以表示具有与其它形状边缘相邻的边缘的形状。 然后指定相邻节点之间的每个连接的当前容量。 电连接到不正确连接的多边形的两个节点被选择并用作网络流分析算法的参数。 该算法确定了高流量由具有最低电流容量的三角形或梯形决定的高密度区域。 高密度区域被标记为可能存在短路的点。 然后可以调查这些标记点以确认它们是否是短路。

公开(公告)号：US08701058B2

公开(公告)日：2014-04-15

申请号：US12817727

申请日：2010-06-17

申请人： Vyacheslav L. Zavadsky ,  Edward Keyes

发明人： Vyacheslav L. Zavadsky ,  Edward Keyes

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The current invention uses structural data mining methods and systems, combined with partitioning hints and heuristics, to locate high level library functional blocks in a gate level netlist of an integrated circuit (IC). In one embodiment of the invention, the library is created by synthesizing various design blocks and constraints. The method supports characterization matching between a netlist and a library, between libraries and between netlists. The data mining method described herein uses a subgraph growing method to progressively characterize the graph representation of the netlist of the IC. In one embodiment of the invention, alternative hashing is used to perform subgraph characterization. Further, the located high level functional blocks may be used to substitute the corresponding portions of the target netlist having the matched characterizations, and may be annotated accordingly in the resulting netlist.

摘要翻译： 本发明使用结构数据挖掘方法和系统，结合分区提示和启发式方法来定位集成电路（IC）的门级网表中的高级库功能块。 在本发明的一个实施例中，通过合成各种设计块和约束来创建库。 该方法支持网表和库之间，库之间和网表之间的表征匹配。 本文描述的数据挖掘方法使用子图生长方法逐渐表征IC的网表的图形表示。 在本发明的一个实施例中，替代散列用于执行子图表征。 此外，所定位的高级功能块可以用于替换具有匹配特征的目标网表的对应部分，并且可以在所得到的网表中相应地注释。

公开(公告)号：US20090092285A1

公开(公告)日：2009-04-09

申请号：US12029199

申请日：2008-02-11

申请人： Edward Keyes ,  Vyacheslav L. Zavadsky

发明人： Edward Keyes ,  Vyacheslav L. Zavadsky

IPC分类号： G06K9/00

CPC分类号： G06T7/0004 ,  G06T2207/30148

摘要： A schematic diagram detailing a circuit that was reverse engineered from a plurality of images taken of the circuit is provided. The schematic diagram includes at least one circuit element that was represented as an object in at least one of the plurality of images, such that signal continuity information was determined through local tracing of connectivity between a first image and a second image of the plurality of images. A method of tracing the connectivity within the plurality of images to produce the schematic diagram is also disclosed.

摘要翻译： 提供了详细描述从电路取得的多个图像中反向工程的电路的示意图。 示意图包括至少一个电路元件，其被表示为多个图像中的至少一个图像中的对象，使得信号连续性信息通过对多个图像的第一图像和第二图像之间的连通性的局部跟踪来确定 。 还公开了一种跟踪多个图像内的连接以产生示意图的方法。

公开(公告)号：US20080317327A1

公开(公告)日：2008-12-25

申请号：US12200968

申请日：2008-08-29

申请人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

发明人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G01R31/31704 ,  G01R31/318357 ,  G06T7/74 ,  G06T2207/30148

摘要： The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

摘要翻译： 本发明涉及一种确定IC布局图像中的标准单元的位置的计算上有效的方法。 初始步骤提取并表征图像的兴趣点。 执行可能的标准单元位置的粗略定位，并且基于提取的标准单元的实例与图像中的剩余兴趣点的兴趣点的比较。 在包括粗匹配和精细匹配的可能位置的列表上进行更刚性的比较。 粗匹配导致可能位置的最后一个列表。 精细比赛会在模板和候选名单之间进行比较。 进行进一步的滤波以消除噪声和纹理变化的影响，并且生成结果的统计以实现标准单元在IC布局上的位置。

公开(公告)号：US20100325593A1

公开(公告)日：2010-12-23

申请号：US12817727

申请日：2010-06-17

申请人： Vyacheslav L. Zavadsky ,  Edward Keyes

发明人： Vyacheslav L. Zavadsky ,  Edward Keyes

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The current invention uses structural data mining methods and systems, combined with partitioning hints and heuristics, to locate high level library functional blocks in a gate level netlist of an integrated circuit (IC). In one embodiment of the invention, the library is created by synthesizing various design blocks and constraints. The method supports characterization matching between a netlist and a library, between libraries and between netlists. The data mining method described herein uses a subgraph growing method to progressively characterize the graph representation of the netlist of the IC. In one embodiment of the invention, alternative hashing is used to perform subgraph characterization. Further, the located high level functional blocks may be used to substitute the corresponding portions of the target netlist having the matched characterizations, and may be annotated accordingly in the resulting netlist.

摘要翻译： 本发明使用结构数据挖掘方法和系统，结合分区提示和启发式方法来定位集成电路（IC）的门级网表中的高级库功能块。 在本发明的一个实施例中，通过合成各种设计块和约束来创建库。 该方法支持网表和库之间，库之间和网表之间的表征匹配。 本文描述的数据挖掘方法使用子图生长方法逐渐表征IC的网表的图形表示。 在本发明的一个实施例中，替代散列用于执行子图表征。 此外，所定位的高级功能块可以用于替换具有匹配特征的目标网表的对应部分，并且可以在所得到的网表中相应地注释。

公开(公告)号：US08606041B2

公开(公告)日：2013-12-10

申请号：US12029199

申请日：2008-02-11

申请人： Edward Keyes ,  Vyacheslav L. Zavadsky

发明人： Edward Keyes ,  Vyacheslav L. Zavadsky

IPC分类号： G06K9/00 ,  G06K9/36

CPC分类号： G06T7/0004 ,  G06T2207/30148

摘要： A schematic diagram detailing a circuit that was reverse engineered from a plurality of images taken of the circuit is provided. The schematic diagram includes at least one circuit element that was represented as an object in at least one of the plurality of images, such that signal continuity information was determined through local tracing of connectivity between a first image and a second image of the plurality of images. A method of tracing the connectivity within the plurality of images to produce the schematic diagram is also disclosed.

摘要翻译： 提供了详细描述从电路取得的多个图像中反向工程的电路的示意图。 示意图包括至少一个电路元件，其被表示为多个图像中的至少一个图像中的对象，使得信号连续性信息通过对多个图像的第一图像和第二图像之间的连接性的局部跟踪来确定 。 还公开了一种跟踪多个图像内的连接以产生示意图的方法。

公开(公告)号：US07643665B2

公开(公告)日：2010-01-05

申请号：US10929798

申请日：2004-08-31

申请人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

发明人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G01R31/31704 ,  G01R31/318357 ,  G06T7/74 ,  G06T2207/30148

摘要： The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

摘要翻译： 本发明涉及一种确定IC布局图像中的标准单元的位置的计算上有效的方法。 初始步骤提取并表征图像的兴趣点。 执行可能的标准单元位置的粗略定位，并且基于提取的标准单元的实例与图像中的剩余兴趣点的兴趣点的比较。 在包括粗匹配和精细匹配的可能位置的列表上进行更刚性的比较。 粗匹配导致可能位置的最后一个列表。 精细比赛会在模板和候选名单之间进行比较。 进行进一步的滤波以消除噪声和纹理变化的影响，并且生成结果的统计以实现标准单元在IC布局上的位置。

公开(公告)号：US07580557B2

公开(公告)日：2009-08-25

申请号：US12200968

申请日：2008-08-29

申请人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

发明人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G01R31/31704 ,  G01R31/318357 ,  G06T7/74 ,  G06T2207/30148

摘要： The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

摘要翻译： 本发明涉及一种确定IC布局图像中的标准单元的位置的计算上有效的方法。 初始步骤提取并表征图像的兴趣点。 执行可能的标准单元位置的粗略定位，并且基于提取的标准单元的实例与图像中的剩余兴趣点的兴趣点的比较。 在包括粗匹配和精细匹配的可能位置的列表上进行更刚性的比较。 粗匹配导致可能位置的最后一个列表。 精细比赛会在模板和候选名单之间进行比较。 进行进一步的滤波以消除噪声和纹理变化的影响，并且生成结果的统计以实现标准单元在IC布局上的位置。

公开(公告)号：US07873203B2

公开(公告)日：2011-01-18

申请号：US12200975

申请日：2008-08-29

申请人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

发明人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G01R31/31704 ,  G01R31/318357 ,  G06T7/74 ,  G06T2207/30148

摘要： The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

摘要翻译： 本发明涉及一种确定IC布局图像中的标准单元的位置的计算上有效的方法。 初始步骤提取并表征图像的兴趣点。 执行可能的标准单元位置的粗略定位，并且基于提取的标准单元的实例与图像中的剩余兴趣点的兴趣点的比较。 在包括粗匹配和精细匹配的可能位置的列表上进行更刚性的比较。 粗匹配导致可能位置的最后一个列表。 精细比赛会在模板和候选名单之间进行比较。 进行进一步的滤波以消除噪声和纹理变化的影响，并且生成结果的统计以实现标准单元在IC布局上的位置。

公开(公告)号：US20080317328A1

公开(公告)日：2008-12-25

申请号：US12200975

申请日：2008-08-29

申请人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

发明人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G01R31/31704 ,  G01R31/318357 ,  G06T7/74 ,  G06T2207/30148

摘要： The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.