Power limiting time delay circuit

    公开(公告)号:US20050140344A1

    公开(公告)日:2005-06-30

    申请号:US11059838

    申请日:2005-02-17

    申请人: Edward Wenzel

    发明人: Edward Wenzel

    摘要: A power limiting circuit for power supply that is controlled by a power supply control module includes a shunt regulator having a reference input operatively connected to a voltage input that receives a voltage representative of the power supply control module connected thereto. The shunt regulator is biased on when the voltage at the reference input increases above a reference voltage established at the voltage input. A transistor is operatively connected to the shunt regulator and to an output operatively connected to the power supply control module and has a voltage that is representative of voltage operating the power supply control module. The transistor is biased on from the shunt regulator such that the shunt regulator and transistor form a latch when the voltage at the output reduces below an off voltage level to turn off the power supply, dropping the input voltage, and restarting the power supply in a restart cycle.