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    Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications
    3.
    发明授权
    Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications 有权
    通过增强的节点间通信来加速线路排他性返回到给定处理器的方法和过程

    公开(公告)号：US08001328B2

    公开(公告)日：2011-08-16

    申请号：US12021378

    申请日：2008-01-29

    申请人： Sebastian C. Burckhardt ,  Arthur J. O'Neill ,  Vesselina K. Papazova ,  Craig R. Walters

    发明人： Sebastian C. Burckhardt ,  Arthur J. O'Neill ,  Vesselina K. Papazova ,  Craig R. Walters

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F2212/1016

    摘要： A method and apparatus in which the observability of cross-invalidates requests within remote nodes is controlled at the time of a partial response generation, when a remote request initially checks/snoops the directory state of the remote node, but before such the time that the cross-invalidate request is actually sent to the processors on a given node. If all of the remote nodes in the system indicate that the cross-invalidates could be sent during an initial directory snoop, the requesting node is able to return full exclusivity to a given cache line to a requesting processor at the time when it receives all of the partial responses, instead of having to wait for the final responses from each of the remote nodes within the system.

    摘要翻译： 当远程请求最初检查/窥探远程节点的目录状态时，而在远程节点的时间之前，在部分响应生成时控制远程节点内的交叉无效请求的可观察性的方法和装置， 交叉无效请求实际上发送给给定节点上的处理器。 如果系统中的所有远程节点指示可以在初始目录窥探期间发送交叉无效信息，则请求节点能够在给定的缓存行接收到所有请求的处理器时向所请求的处理器返回完整的排他性 部分响应，而不必等待系统内每个远程节点的最终响应。

    Cache coherency protocol with built in avoidance for conflicting responses
    6.
    发明授权
    Cache coherency protocol with built in avoidance for conflicting responses 失效
    缓存一致性协议内置避免冲突的响应

    公开(公告)号：US08250308B2

    公开(公告)日：2012-08-21

    申请号：US12031977

    申请日：2008-02-15

    申请人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

    发明人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831

    摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership state of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.

    摘要翻译： 该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及 指定地址的所有权状态，将目标行的状态返回到请求节点并形成组合响应，并将组合的响应广播到每个远程节点。 在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是 源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

    Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching
    7.
    发明授权
    Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching 有权
    方法，系统和计算机程序产品，用于防止具有推测性内存提取的多节点系统中的锁定和停顿条件

    公开(公告)号：US07934059B2

    公开(公告)日：2011-04-26

    申请号：US12021781

    申请日：2008-01-29

    申请人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

    发明人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831 ,  G06F2212/507

    摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.

    摘要翻译： 一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出 对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到 解决冲突的点，而不发出另一个推测性的内存提取请求。 随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PREVENTING LOCKOUT AND STALLING CONDITIONS IN A MULTI-NODE SYSTEM WITH SPECULATIVE MEMORY FETCHING
    8.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PREVENTING LOCKOUT AND STALLING CONDITIONS IN A MULTI-NODE SYSTEM WITH SPECULATIVE MEMORY FETCHING 有权
    方法，系统和计算机程序产品，用于在具有分析存储器故障的多节点系统中防止闭锁和停放条件

    公开(公告)号：US20090193198A1

    公开(公告)日：2009-07-30

    申请号：US12021781

    申请日：2008-01-29

    申请人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

    发明人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831 ,  G06F2212/507

    摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.

    摘要翻译： 一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出 对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到 解决冲突的点，而不发出另一个推测性的内存提取请求。 随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

    Maintaining cache coherence in a multi-node, symmetric multiprocessing computer
    9.
    发明授权
    Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效
    在多节点对称多处理计算机中维护高速缓存一致性

    公开(公告)号：US08762651B2

    公开(公告)日：2014-06-24

    申请号：US12821578

    申请日：2010-06-23

    申请人： Michael A. Blake ,  Garrett M. Drapala ,  Pak-Kin Mak ,  Vesselina K. Papazova ,  Craig R. Walters

    发明人： Michael A. Blake ,  Garrett M. Drapala ,  Pak-Kin Mak ,  Vesselina K. Papazova ,  Craig R. Walters

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0815 ,  G06F12/0831 ,  G06F12/084

    摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.

    摘要翻译： 在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由所述第一计算节点向高速缓存未命中的高速缓存发送对所述高速缓存行的请求; 如果至少两个计算节点具有高速缓存行的正确副本，则选择哪个计算节点将高速缓存行的正确副本发送到第一节点，以及从所选择的计算节点向第一节点发送正确的副本 的缓存行; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

    Maintaining cache coherence in a multi-node, symmetric multiprocessing computer
    10.
    发明授权
    Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效
    在多节点对称多处理计算机中维护高速缓存一致性

    公开(公告)号：US08423736B2

    公开(公告)日：2013-04-16

    申请号：US12816464

    申请日：2010-06-16

    申请人： Michael A. Blake ,  Garrett M. Drapala ,  Pak-Kin Mak ,  Vesselina K. Papazova ,  Craig R. Walters

    发明人： Michael A. Blake ,  Garrett M. Drapala ,  Pak-Kin Mak ,  Vesselina K. Papazova ,  Craig R. Walters

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0833

    摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.

    摘要翻译： 在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。