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公开(公告)号：US08509321B2
公开(公告)日：2013-08-13
申请号：US11021514
申请日：2004-12-23
IPC分类号： H04K1/10
CPC分类号： H04L5/1423 , H04L5/1438 , H04L5/1461
摘要： A memory system with a simultaneous bi-directional link includes a controller, a memory device and a set of signal lines coupled to the controller and the memory device. Simultaneous communication between the controller and the memory device on the set of signal lines uses a first band of frequencies, and between the memory device and the controller on the set of signal lines uses a second band of frequencies. The controller is configured to dynamically adjust the first band of frequencies based on a predetermined data rate between the controller and the memory device and to dynamically adjust the second band of frequencies based on a predetermined data rate between the memory device and the controller.
摘要翻译： 具有同时双向链路的存储器系统包括控制器，存储器件和耦合到控制器和存储器件的一组信号线。 控制器与信号线组上的存储器件之间的同时通信使用第一频带，并且存储器件与信号线组上的控制器之间使用第二频带。 控制器被配置为基于控制器和存储设备之间的预定数据速率来动态地调整第一频带，并且基于存储器设备和控制器之间的预定数据速率来动态调整第二频带。
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公开(公告)号：US20060140287A1
公开(公告)日：2006-06-29
申请号：US11021514
申请日：2004-12-23
IPC分类号： H04K1/10
CPC分类号： H04L5/1423 , H04L5/1438 , H04L5/1461
摘要： A memory system with a simultaneous bi-directional link includes a controller, a memory device and a set of signal lines coupled to the controller and the memory device. Simultaneous communication between the controller and the memory device on the set of signal lines uses a first band of frequencies, and between the memory device and the controller on the set of signal lines uses a second band of frequencies. The controller is configured to dynamically adjust the first band of frequencies based on a predetermined data rate between the controller and the memory device and to dynamically adjust the second band of frequencies based on a predetermined data rate between the memory device and the controller.
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公开(公告)号：US20090031091A1
公开(公告)日：2009-01-29
申请号：US12137935
申请日：2008-06-12
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data.
摘要翻译： 描述了调整存储器控制器上的写入操作的定时的系统。 该系统通过观察存储器控制器上的读取数据的定时漂移，然后基于观察到的读取数据的定时漂移来调整存储器控制器上的写入操作的定时。
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公开(公告)号：US08341450B2
公开(公告)日：2012-12-25
申请号：US12137935
申请日：2008-06-12
IPC分类号： G06F13/42
CPC分类号： G06F13/1689
摘要： A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data.
摘要翻译： 描述了调整存储器控制器上的写入操作的定时的系统。 该系统通过观察存储器控制器上的读取数据的定时漂移，然后基于观察到的读取数据的定时漂移来调整存储器控制器上的写入操作的定时。
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公开(公告)号：US08325861B2
公开(公告)日：2012-12-04
申请号：US13341612
申请日：2011-12-30
IPC分类号： H04L25/08
摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.
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公开(公告)号：US20100239057A1
公开(公告)日：2010-09-23
申请号：US12787352
申请日：2010-05-25
IPC分类号： H04B1/10
摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.
摘要翻译： 电路包括频率合成器，耦合到频率合成器的N相混频器，多个接收器和校准电路。 频率合成器是接收参考时钟信号，并输出主时钟信号。 N相混频器中的相应的混频器将输出具有相应相位的相应次级时钟信号。 多个接收机中的相应接收机耦合到N相混合器中的两个，并且在相应的时间是根据耦合到相应接收机的两个相位混合器之一的相应辅助时钟信号接收数据。 校准电路是通过调整相位相位混合器的次级时钟信号的相位来校准由N相混频器中的各个相位混频器输出的次级时钟信号。
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公开(公告)号：US20120099678A1
公开(公告)日：2012-04-26
申请号：US13341612
申请日：2011-12-30
摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.
摘要翻译： 电路包括频率合成器，耦合到频率合成器的N相混频器，多个接收器和校准电路。 频率合成器是接收参考时钟信号，并输出主时钟信号。 N相混频器中的相应的混频器将输出具有相应相位的相应次级时钟信号。 多个接收机中的相应接收机耦合到N相混合器中的两个，并且在相应的时间是根据耦合到相应接收机的两个相位混合器之一的相应辅助时钟信号接收数据。 校准电路是通过调整相位相位混合器的次级时钟信号的相位来校准由N相混频器中的各个相位混频器输出的次级时钟信号。
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公开(公告)号：US08121233B2
公开(公告)日：2012-02-21
申请号：US12787352
申请日：2010-05-25
IPC分类号： H04B1/10
摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.
摘要翻译： 电路包括频率合成器，耦合到频率合成器的N相混频器，多个接收器和校准电路。 频率合成器是接收参考时钟信号，并输出主时钟信号。 N相混频器中的相应的混频器将输出具有相应相位的相应次级时钟信号。 多个接收机中的相应接收机耦合到N相混合器中的两个，并且在相应的时间是根据耦合到相应接收机的两个相位混合器之一的相应辅助时钟信号接收数据。 校准电路是通过调整相位相位混合器的次级时钟信号的相位来校准由N相混频器中的各个相位混频器输出的次级时钟信号。
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9.发明申请公开(公告)号：US20100281289A1
公开(公告)日：2010-11-04
申请号：US12743075
申请日：2008-11-14
申请人： Kun-Yung Chang , Jie Shen , Hae-Chang Lee , Fariborz Assaderaghi , Richard E. Perego , Jung-Hoon Chun
发明人： Kun-Yung Chang , Jie Shen , Hae-Chang Lee , Fariborz Assaderaghi , Richard E. Perego , Jung-Hoon Chun
CPC分类号： G06F13/1689
摘要： A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation.
摘要翻译： 描述了具有发送和接收操作模式的位分片电路。 所述位片电路包括：第一发射电路和在第一时钟域中操作的第一接收电路，其中所述第一电路接收第一时钟信号; 第二发送电路和在第二时钟域中操作的第二接收电路，其中所述第二电路接收第二时钟信号; 发射转换电路和接收转换电路，所述发射转换电路将所述第一发射电路耦合到所述第二发射电路，所述接收转换电路将所述第一接收电路耦合到所述第二接收电路，其中所述转换电路接收所述第一和第二时钟信号; 以及产生所述第二时钟信号的单相混频器，其中所述第二时钟信号具有所述发送操作模式中的第一相位和所述接收操作模式中的第二相位。
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公开(公告)号：US20100235554A1
公开(公告)日：2010-09-16
申请号：US12679461
申请日：2008-09-05
IPC分类号： G06F13/14
CPC分类号： G06F13/385
摘要： Embodiments of an apparatus are described. An interface circuit in this apparatus receives or transmits digital signals on a bus and is configured to alternatively operate as either a data-bus interface circuit or a control-bus interface circuit in dependence upon a mode setting stored in a register. For example, the interface circuit may be pre-configured to interpret a line of an external bus as either a data line or a control line in accordance with the stored mode setting. Moreover, the stored mode setting may be dynamically configured (e.g., reprogrammed) during operation of the interface circuit so that subsequent digital signals are subsequently handled in accordance with a new mode setting.
摘要翻译： 描述装置的实施例。 该装置中的接口电路在总线上接收或发送数字信号，并且被配置为根据存储在寄存器中的模式设置交替地操作数据总线接口电路或控制总线接口电路。 例如，接口电路可以被预先配置为根据存储的模式设置将外部总线的线路解释为数据线或控制线。 此外，存储模式设置可以在接口电路的操作期间被动态配置（例如，重新编程），使得随后的数字信号随后根据新的模式设置进行处理。
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