公开(公告)号：US20140189308A1

公开(公告)日：2014-07-03

申请号：US13731006

申请日：2012-12-29

申请人： Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Brett L. Toll ,  Mark J. Charney ,  Milind B. Girkar

发明人： Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Brett L. Toll ,  Mark J. Charney ,  Milind B. Girkar

IPC分类号： G06F9/30

CPC分类号： G06F9/30021 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3838 ,  G06F9/3887

摘要： Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data fields to store a variable second plurality of bits to store a conflict mask having a mask bit for each offset. Responsive to decoding a vector conflict instruction, execution units compare the offset in each data field with every less significant data field to determine if they hold a matching offset, and in corresponding conflict masks in the destination register, set any mask bits corresponding to a less significant data field with a matching offset. Vector address conflict detection can be used with variable sized elements and to generate conflict masks to resolve dependencies in gather-modify-scatter SIMD operations.

摘要翻译： 指令和逻辑提供SIMD地址冲突检测功能。 一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段存储用于存储器中的数据元素的偏移量。 目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储可变的第二多个位以存储具有每个偏移的掩码位的冲突掩码。 响应于对向量冲突指令进行解码，执行单元将每个数据字段中的偏移量与每个较不重要的数据字段进行比较，以确定它们是否保持匹配的偏移，并且在目标寄存器中的相应冲突掩码中，设置对应于较少 具有匹配偏移的重要数据字段。 向量地址冲突检测可以与可变大小的元素一起使用，并生成冲突掩码来解决收集修改分散SIMD操作中的依赖关系。

公开(公告)号：US20140189307A1

公开(公告)日：2014-07-03

申请号：US13731005

申请日：2012-12-29

申请人： Robert Valentine ,  Mark J. Charney ,  Jesus Corbal ,  Milind B. Girkar ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Brett L. Toll

发明人： Robert Valentine ,  Mark J. Charney ,  Jesus Corbal ,  Milind B. Girkar ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Brett L. Toll

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F7/607 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3887 ,  H03M7/20

摘要： Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store a variable second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of bits set to one for corresponding data fields. Responsive to decoding a vector population count instruction, execution units count the number of bits set to one for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector population count instructions can be used with variable sized elements and conflict masks to generate iteration counts and completion masks to be used each iteration to resolve dependencies in gather-modify-scatter SIMD operations.

摘要翻译： 指令和逻辑提供SIMD地址冲突解决与向量群体计数功能。 一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段用于存储可变的第二多个位。 目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储为相应的数据字段设置为1的位数的计数。 响应于对向量群体计数指令进行解码，执行单元对寄存器中的每个数据字段设置为1的位数进行计数，并将计数存储在第一目的地寄存器的相应数据字段中。 矢量人口计数指令可用于可变大小的元素和冲突掩码，以生成迭代计数和完成掩码，以便在每次迭代中使用以解决聚集修改散射SIMD操作中的依赖关系。

公开(公告)号：US20140149802A1

公开(公告)日：2014-05-29

申请号：US13688544

申请日：2012-11-29

申请人： Christopher J. Hughes ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine

发明人： Christopher J. Hughes ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine

IPC分类号： G06F11/00

CPC分类号： G06F11/004 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3865 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772

摘要： A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.

摘要翻译： 处理器包括执行单元，耦合到执行单元的故障掩模以及耦合到执行单元的抑制掩模。 故障掩码是存储第一多个比特值以指示多元素向量的哪些元素具有响应于在执行单元中的元素上的指令的执行而产生的相关联的故障。 抑制掩模是存储第二多个位值，以指示哪个元件将被抑制相关联的故障。 所述处理器还包括计数器逻辑，以响应于与所述第一元件相关联并从所述故障掩模接收到的第一故障的指示来增加计数器，以及与所述第一元件相关联并从所述抑制掩码接收到的第一抑制的指示。 其他实施例被描述为所要求保护的。

公开(公告)号：US20160179530A1

公开(公告)日：2016-06-23

申请号：US14582007

申请日：2014-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Bret L. Toll ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Bret L. Toll ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30036 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/30018

摘要： In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.

摘要翻译： 在几个实施例中，指令集架构的向量扩展包括执行饱和有符号和无符号整数加法的指令。 在一个实施例中，提供了带符号饱和的向量有符号整数加法。 在一个实施例中，提供了具有无符号饱和度的向量无符号整数加法。 在一个实施例中，带符号和无符号指令都支持打包的双字和四字整数。

公开(公告)号：US20170192781A1

公开(公告)日：2017-07-06

申请号：US14984124

申请日：2015-12-30

申请人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

发明人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30192 ,  G06F9/3455

摘要： Detailed herein are systems, apparatuses, and methods for strided loads. In an embodiment, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields a starting source memory address operand and a starting destination register operand; and execution circuitry to execute the decoded instruction to extract data elements of a defined number of types from contiguous memory beginning at the starting source memory address and, for each type, store the extracted data elements in a packed data register dedicated to that type beginning with starting destination register operand.

公开(公告)号：US20170192780A1

公开(公告)日：2017-07-06

申请号：US14984078

申请日：2015-12-30

申请人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

发明人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30192

摘要： Embodiments of systems, apparatuses, and method for getting even or odd data elements are described. For example, in some embodiments, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand.

公开(公告)号：US09785442B2

公开(公告)日：2017-10-10

申请号：US14582897

申请日：2014-12-24

申请人： Elmoustapha Ould-Ahmed-Vall ,  Christopher J. Hughes ,  Robert Valentine ,  Milind B. Girkar

发明人： Elmoustapha Ould-Ahmed-Vall ,  Christopher J. Hughes ,  Robert Valentine ,  Milind B. Girkar

IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/46

CPC分类号： G06F9/3016 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/34 ,  G06F9/3455 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467

摘要： Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address and an operand to store a stride value, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.

公开(公告)号：US08972698B2

公开(公告)日：2015-03-03

申请号：US12976616

申请日：2010-12-22

申请人： Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

发明人： Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3838

摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

摘要翻译： 描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。 处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

公开(公告)号：US20140344553A1

公开(公告)日：2014-11-20

申请号：US13898189

申请日：2013-05-20

申请人： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

发明人： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345

摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

摘要翻译： 根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

公开(公告)号：US20140281401A1

公开(公告)日：2014-09-18

申请号：US13840809

申请日：2013-03-15

申请人： Christopher J. Hughes ,  Mark J. Charney ,  Jesus Corbal ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed_Vall ,  Bret L. Toll ,  Robert Valentine

发明人： Christopher J. Hughes ,  Mark J. Charney ,  Jesus Corbal ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed_Vall ,  Bret L. Toll ,  Robert Valentine

IPC分类号： G06F9/30

CPC分类号： G06F9/30152 ,  G06F9/30018 ,  G06F9/30036

摘要： The execution of a KZBTZ finds a trailing least significant zero bit position in an first input mask and sets an output mask to have the values of the first input mask, but with all bit positions closer to the most significant bit position than the trailing least significant zero bit position in an first input mask set to zero. In some embodiments, a second input mask is used as a writemask such that bit positions of the first input mask are not considered in the trailing least significant zero bit position calculation depending upon a corresponding bit position in the second input mask.

摘要翻译： KZBTZ的执行在第一输入掩码中找到尾随的最低有效零位位置，并将输出掩码设置为具有第一输入掩码的值，但是所有位位置都比接近最低有效位更靠近最高有效位位置 第一个输入掩码中的零位位置设置为零。 在一些实施例中，使用第二输入掩码作为写掩码，使得根据第二输入掩码中的相应位位置，在尾随最低有效零位位置计算中不考虑第一输入掩码的位位置。