公开(公告)号：US20140189296A1

公开(公告)日：2014-07-03

申请号：US13993323

申请日：2011-12-14

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Andrey Naraikin ,  Suleyman Sair ,  Asaf Hargil ,  Miland B. Girkar ,  Bret T. Toll ,  Mark J. Charney

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Andrey Naraikin ,  Suleyman Sair ,  Asaf Hargil ,  Miland B. Girkar ,  Bret T. Toll ,  Mark J. Charney

IPC分类号： G06F9/38

CPC分类号： G06F9/3887 ,  G06F8/4441 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/3013 ,  G06F9/325 ,  G06F9/3818 ,  G06F9/3824

摘要： A loop remainder mask instruction indicates a current iteration count of a loop as a first operand, an iteration limit of a loop as a second operand, and a destination. The loop contains iterations and each iteration includes a data element of the array. A processor receives the loop remainder mask instruction, decodes the instruction for execution, and stores a result of the execution in the destination. The result indicates a number of data elements of the array past an end of a preceding portion of the array that are to be handled separately from the preceding portion, the end of the preceding portion being where the current iteration count is recorded.

摘要翻译： 循环余数掩码指令指示作为第一操作数的循环的当前迭代计数，作为第二操作数的循环的迭代限制以及目的地。 循环包含迭代，每次迭代都包含数组的数据元素。 处理器接收循环余数掩码指令，解码执行指令，并将执行结果存储在目的地。 结果表示阵列的数据元素数目超过阵列的前一部分的结尾，与前一部分分开处理，前一部分的结尾是当前迭代计数的记录。

公开(公告)号：US09632980B2

公开(公告)日：2017-04-25

申请号：US13976435

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Suleyman Sair

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Suleyman Sair

IPC分类号： G06F9/30 ,  G06F15/80

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F15/8092

摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

公开(公告)号：US20130290672A1

公开(公告)日：2013-10-31

申请号：US13976435

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Suleyman Sair

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Suleyman Sair

IPC分类号： G06F15/80

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F15/8092

摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

摘要翻译： 描述了具有指令执行逻辑电路的装置。 指令执行逻辑电路具有输入向量元素路由电路，以对三个不同的指令中的每一个执行以下操作：对于多个输出向量元素位置中的每一个，将输入向量元素从多个 可用于输出输出向量元素的输入向量元素位置。 输出向量元素和每个输入向量元素位置是三个不同指令的三个可用位宽之一。 该装置还包括耦合到输入向量元素路由电路以屏蔽由输入向量路由选择元件电路产生的数据结构的掩蔽层电路。 掩蔽层电路被设计为以与三个可用位宽对应的三个不同的粒度级别进行掩蔽。

公开(公告)号：US09658850B2

公开(公告)日：2017-05-23

申请号：US13976993

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30029 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

公开(公告)号：US09619236B2

公开(公告)日：2017-04-11

申请号：US13976992

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3802

摘要： An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

公开(公告)号：US20140149802A1

公开(公告)日：2014-05-29

申请号：US13688544

申请日：2012-11-29

申请人： Christopher J. Hughes ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine

发明人： Christopher J. Hughes ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine

IPC分类号： G06F11/00

CPC分类号： G06F11/004 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3865 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772

摘要： A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.

摘要翻译： 处理器包括执行单元，耦合到执行单元的故障掩模以及耦合到执行单元的抑制掩模。 故障掩码是存储第一多个比特值以指示多元素向量的哪些元素具有响应于在执行单元中的元素上的指令的执行而产生的相关联的故障。 抑制掩模是存储第二多个位值，以指示哪个元件将被抑制相关联的故障。 所述处理器还包括计数器逻辑，以响应于与所述第一元件相关联并从所述故障掩模接收到的第一故障的指示来增加计数器，以及与所述第一元件相关联并从所述抑制掩码接收到的第一抑制的指示。 其他实施例被描述为所要求保护的。

公开(公告)号：US20140059322A1

公开(公告)日：2014-02-27

申请号：US13996800

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L Toll ,  Mark J Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L Toll ,  Mark J Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F15/80

摘要： An apparatus and method are described for broadcasting from a general purpose source register to a destination vector register. For example, a method according to one embodiment includes the following operations: selecting data element position N within the destination vector register to be updated; broadcasting a set of data from the general purpose source register to data element position N within the destination vector register if a mask indicator is set to a first indication; and either copying zeroes to data element position N within the destination vector register or maintaining existing values stored within data element position N within the destination vector register if the mask indicator is set to a second indication.

摘要翻译： 描述了用于从通用源寄存器到目的地向量寄存器的广播的装置和方法。 例如，根据一个实施例的方法包括以下操作：选择要更新的目的地向量寄存器内的数据元素位置N; 如果将掩码指示符设置为第一指示，则将一组数据从通用源寄存器传送到目的地向量寄存器内的数据元素位置N; 并且如果掩模指示符被设置为第二指示，则将零值复制到目的地向量寄存器内的数据元素位置N，或者保持存储在目的地向量寄存器内的数据元素位置N内的现有值。

公开(公告)号：US20160179530A1

公开(公告)日：2016-06-23

申请号：US14582007

申请日：2014-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Bret L. Toll ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Bret L. Toll ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30036 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/30018

摘要： In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.

摘要翻译： 在几个实施例中，指令集架构的向量扩展包括执行饱和有符号和无符号整数加法的指令。 在一个实施例中，提供了带符号饱和的向量有符号整数加法。 在一个实施例中，提供了具有无符号饱和度的向量无符号整数加法。 在一个实施例中，带符号和无符号指令都支持打包的双字和四字整数。

公开(公告)号：US20130290687A1

公开(公告)日：2013-10-31

申请号：US13976993

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30029 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

摘要翻译： 描述了具有指令执行逻辑电路的装置。 指令执行逻辑电路具有输入向量元素路由电路，以对三个不同的指令中的每一个执行以下操作：对于多个输出向量元素位置中的每一个，将输入向量元素从多个 可用于输出输出向量元素的输入向量元素位置。 输出向量元素和每个输入向量元素位置是三个不同指令的三个可用位宽之一。 该装置还包括耦合到输入向量元素路由电路以屏蔽由输入向量路由选择元件电路产生的数据结构的掩蔽层电路。 掩蔽层电路被设计为以与三个可用位宽对应的三个不同的粒度级别进行掩蔽。

公开(公告)号：US09588764B2

公开(公告)日：2017-03-07

申请号：US13976998

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30149 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30145

摘要： An apparatus is described that includes instruction execution circuitry to execute first, second, third, and fourth instructions, the first and second instructions select a first group of input vector elements from one of multiple first non-overlapping sections of respective first and second input vectors. Each of the multiple first non-overlapping sections have a same bit width as the first group. Both the third and fourth instructions select a second group of input vector elements from one of multiple second non overlapping sections of respective third and fourth input vectors. The second group has a second bit width that is larger than the first bit width. Each of multiple second non overlapping sections have a same bit width as the second group. The apparatus includes masking layer circuitry to mask the first and second groups at a first granularity and second granularity.

摘要翻译： 描述了一种装置，其包括执行第一，第二，第三和第四指令的指令执行电路，第一和第二指令从第一和第二输入向量的多个第一非重叠部分之一中选择第一组输入向量元素 。 多个第一非重叠部分中的每一个具有与第一组相同的位宽度。 第三和第四指令都从相应的第三和第四输入向量的多个第二非重叠部分之一中选择第二组输入向量元素。 第二组具有比第一位宽大的第二位宽度。 多个第二非重叠部分中的每一个具有与第二组相同的位宽度。 该装置包括掩蔽层电路，以第一粒度和第二粒度掩蔽第一和第二组。