公开(公告)号：US08976612B2

公开(公告)日：2015-03-10

申请号：US13666177

申请日：2012-11-01

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Yasutoshi Yamada

IPC: G11C7/02 ,  G11C7/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/06 ,  G11C5/147 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1087 ,  G11C11/4091

Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

公开(公告)号：US08982652B2

公开(公告)日：2015-03-17

申请号：US13675431

申请日：2012-11-13

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Yasutoshi Yamada

IPC: G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C7/06 ,  G11C5/147 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1087 ,  G11C11/4091

Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

Abstract translation: 本发明的单端读出放大器电路包括第一和第二MOS晶体管以及第一和第二预充电电路。 第一MOS晶体管将位线驱动到预定电压并且切换位线和感测节点之间的连接，并且栅极连接到感测节点的第二MOS晶体管经由第一MOS晶体管放大信号。 第一预充电电路将位线预充电到第一电位，而第二预充电电路将感测节点预充电到第二电位。 在感测操作之前，当控制上述栅极电压降低时，位线被驱动到预定电压。 适当地设定预定电压，使得可以在电荷转移/分配模式之间的变化点附近获得在高电平和低电平之间的感测节点处的所需电压差。