公开(公告)号：US08982652B2

公开(公告)日：2015-03-17

申请号：US13675431

申请日：2012-11-13

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Yasutoshi Yamada

IPC: G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C7/06 ,  G11C5/147 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1087 ,  G11C11/4091

Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

Abstract translation: 本发明的单端读出放大器电路包括第一和第二MOS晶体管以及第一和第二预充电电路。 第一MOS晶体管将位线驱动到预定电压并且切换位线和感测节点之间的连接，并且栅极连接到感测节点的第二MOS晶体管经由第一MOS晶体管放大信号。 第一预充电电路将位线预充电到第一电位，而第二预充电电路将感测节点预充电到第二电位。 在感测操作之前，当控制上述栅极电压降低时，位线被驱动到预定电压。 适当地设定预定电压，使得可以在电荷转移/分配模式之间的变化点附近获得在高电平和低电平之间的感测节点处的所需电压差。

公开(公告)号：US08477552B2

公开(公告)日：2013-07-02

申请号：US13716539

申请日：2012-12-17

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya ,  Soichiro Yoshida

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/02 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.

Abstract translation: 半导体存储器件包括存储单元阵列，第一和第二位线，第一和第二放大器以及读出放大器控制电路。 第一读出放大器中的放大元件放大第一位线的信号并将其转换为输出电流。 第二位线经由第一读出放大器选择性地连接到第一位线。 第二读出放大器中的信号电压判定单元确定被提供有输出电流的第二位线的信号电平。 读出放大器控制电路根据在正常操作中的第一定时将上述连接从连接状态切换到断开状态的确定定时来控制放大元件与单元之间的连接，并以相同的方式在一个 在刷新操作中延迟第二定时。

公开(公告)号：US09543953B2

公开(公告)日：2017-01-10

申请号：US13967267

申请日：2013-08-14

Applicant: ELPIDA MEMORY, INC.

Inventor： Soichiro Yoshida

IPC: H03K19/0185 ,  H03K19/017 ,  G11C8/00 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  H01L27/108 ,  H01L29/78

CPC classification number: H03K19/018507 ,  G11C7/1048 ,  G11C11/4091 ,  G11C11/4096 ,  H01L27/10802 ,  H01L29/7841 ,  H03K19/017 ,  H03K2217/0018

Abstract: A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level.

Abstract translation: 半导体器件包括：第一电路节点，被提供有在第一和第二逻辑电平之间变化的第一信号;第二电路节点，被提供有在第一和第二逻辑电平之间变化的第二信号，第三电路节点，具有栅极的第一晶体管 电连接到第一电路节点和电连接在第二和第三电路节点之间的源极 - 漏极路径，当第一信号处于第二逻辑电平时，第一晶体管导通，提供有电压电平的第四电路节点为 接近或相同于第二逻辑电平的第二晶体管，以及电连接到第一电路节点的栅极和电连接在第三和第四电路节点之间的源极 - 漏极路径的第二晶体管，当第一晶体管的第一 信号处于第一逻辑电平。

公开(公告)号：US08976612B2

公开(公告)日：2015-03-10

申请号：US13666177

申请日：2012-11-01

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Yasutoshi Yamada

IPC: G11C7/02 ,  G11C7/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/06 ,  G11C5/147 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1087 ,  G11C11/4091

Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

公开(公告)号：US20130328590A1

公开(公告)日：2013-12-12

申请号：US13967267

申请日：2013-08-14

Applicant: Elpida Memory, Inc.

Inventor： Soichiro Yoshida

IPC: H03K19/0185

CPC classification number: H03K19/018507 ,  G11C7/1048 ,  G11C11/4091 ,  G11C11/4096 ,  H01L27/10802 ,  H01L29/7841 ,  H03K19/017 ,  H03K2217/0018

Abstract: A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level.

Abstract translation: 半导体器件包括：第一电路节点，被提供有在第一和第二逻辑电平之间变化的第一信号;第二电路节点，被提供有在第一和第二逻辑电平之间变化的第二信号，第三电路节点，具有栅极的第一晶体管 电连接到第一电路节点和电连接在第二和第三电路节点之间的源极 - 漏极路径，当第一信号处于第二逻辑电平时，第一晶体管导通，提供有电压电平的第四电路节点为 接近或相同于第二逻辑电平的第二晶体管，以及电连接到第一电路节点的栅极和电连接在第三和第四电路节点之间的源极 - 漏极路径的第二晶体管，当第一晶体管的第一 信号处于第一逻辑电平。

公开(公告)号：US08605524B2

公开(公告)日：2013-12-10

申请号：US13653265

申请日：2012-10-16

Applicant: Elpida Memory, Inc.

Inventor： Soichiro Yoshida

IPC: G11C7/00

CPC classification number: G11C7/08 ,  G11C7/04 ,  G11C7/067 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091

Abstract: A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled in series between the second bit line and a first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and supply a control signal to a gate of the second transistor.

Abstract translation: 半导体器件包括存储单元，耦合到存储单元的第一位线，第二位线，包括第一和第二晶体管的第一读出放大器电路，第一晶体管包括耦合到第一位线的栅极，第一晶体管包括第一位线 并且第二晶体管串联耦合在第二位线和第一电压线之间，温度检测电路被配置为检测半导体器件的温度，以及控制电路，被配置为接收温度检测电路的输出并提供控制 信号到第二晶体管的栅极。