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公开(公告)号：US07319061B2
公开(公告)日：2008-01-15
申请号：US11586586
申请日：2006-10-26
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
摘要翻译： 在制造包括具有漏极延伸结构的晶体管的电子器件的方法中，预先获得晶体管的栅电极的尺寸和离子注入条件或用于形成漏极延伸结构的热处理条件之间的对应关系。 该对应性满足晶体管具有给定的阈值电压。 在形成栅电极并测量栅电极的尺寸之后，基于先前获得的对应关系和所测量的栅电极的尺寸来设定用于形成漏极延伸结构的离子注入条件或热处理条件。 用于形成漏极延伸结构的离子注入或热处理在已设定的离子注入条件或热处理条件下进行。
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公开(公告)号：US07282416B2
公开(公告)日：2007-10-16
申请号：US11241950
申请日：2005-10-04
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
摘要翻译： 在制造包括具有漏极延伸结构的晶体管的电子器件的方法中，预先获得晶体管的栅电极的尺寸和离子注入条件或用于形成漏极延伸结构的热处理条件之间的对应关系。 该对应性满足晶体管具有给定的阈值电压。 在形成栅电极并测量栅电极的尺寸之后，基于先前获得的对应关系和所测量的栅电极的尺寸来设定用于形成漏极延伸结构的离子注入条件或热处理条件。 用于形成漏极延伸结构的离子注入或热处理在已设定的离子注入条件或热处理条件下进行。
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公开(公告)号：US20070048918A1
公开(公告)日：2007-03-01
申请号：US11586586
申请日：2006-10-26
IPC分类号： H01L21/8234
CPC分类号： H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
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公开(公告)号：US20060079044A1
公开(公告)日：2006-04-13
申请号：US11241950
申请日：2005-10-04
IPC分类号： H01L21/8234
CPC分类号： H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
摘要翻译： 在制造包括具有漏极延伸结构的晶体管的电子器件的方法中，预先获得晶体管的栅电极的尺寸和离子注入条件或用于形成漏极延伸结构的热处理条件之间的对应关系。 该对应性满足晶体管具有给定的阈值电压。 在形成栅电极并测量栅电极的尺寸之后，基于先前获得的对应关系和所测量的栅电极的尺寸来设定用于形成漏极延伸结构的离子注入条件或热处理条件。 用于形成漏极延伸结构的离子注入或热处理在已设定的离子注入条件或热处理条件下进行。
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5.发明授权公开(公告)号：US07103271B2
公开(公告)日：2006-09-05
申请号：US11000223
申请日：2004-12-01
申请人： Emi Kanazaki , Satoshi Shibata , Fumitoshi Kawase
发明人： Emi Kanazaki , Satoshi Shibata , Fumitoshi Kawase
CPC分类号： H01L21/67248 , H01L21/67115
摘要： A light irradiation heat treatment apparatus and method may use a plane-shaped light irradiation heating component, facing one surface of a workpiece supported in a furnace, to raise the temperature of the workpiece. The temperature of the workpiece is raised by setting an intensity distribution for light irradiated from the light irradiation heating component in accordance with the resistivity of the workpiece. Thereafter, the workpiece is irradiated with light having the set light intensity distribution to raise its temperature.
摘要翻译： 光照射热处理装置和方法可以使用平面形的光照射加热部件，面对被支撑在炉中的工件的一个表面，以提高工件的温度。 通过根据工件的电阻率设定从光照射加热部件照射的光的强度分布来提高工件的温度。 此后，用具有设定的光强度分布的光照射工件以升高其温度。
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6.发明申请公开(公告)号：US20050173386A1
公开(公告)日：2005-08-11
申请号：US11000223
申请日：2004-12-01
申请人： Emi Kanazaki , Satoshi Shibata , Fumitoshi Kawase
发明人： Emi Kanazaki , Satoshi Shibata , Fumitoshi Kawase
CPC分类号： H01L21/67248 , H01L21/67115
摘要： A distribution is given to a light irradiation intensity at a temperature rise process after starting a light irradiation (open loop control process), and temperature variation of the workpiece is reduced, so that thermal stress applied to a workpiece is reduced. A light irradiation heat treatment method for supporting a workpiece in a furnace, and heat-treating the workpiece by means of plane-shaped light irradiation heating means provided so as to face to one surface of the workpiece includes a process for irradiating a light having a flat intensity distribution to the workpiece from the light irradiation heating means and raising the temperature of the workpiece. In the open loop control process after starting the light irradiation, the temperature variation of the workpiece can be reduced by setting the light irradiation intensity for every plurality of areas. It is therefore possible to reduce stress, suppress a characteristic fluctuation of the semiconductor device built in the workpiece without distortion, deformation, warpage, crack or the like, and reduce a defect in reliability.
摘要翻译： 在开始光照射（开环控制处理）之后，在升温过程中给出光照射强度的分布，并减少工件的温度变化，从而降低施加于工件的热应力。 一种用于在炉中支撑工件并且通过设置成面向工件的一个表面的平面形状的光照射加热装置对工件进行热处理的光照射热处理方法包括用于照射具有 从光照射加热装置到工件的平坦强度分布并提高工件的温度。 在开始光照射之后的开环控制处理中，通过设定每多个区域的光照射强度，可以降低工件的温度变化。 因此，可以减少应力，抑制内置在工件中的半导体装置的特征波动，而不产生变形，变形，翘曲，裂纹等，并且减少可靠性的缺陷。
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公开(公告)号：US20060186354A1
公开(公告)日：2006-08-24
申请号：US11353145
申请日：2006-02-14
申请人： Fumitoshi Kawase , Satoshi Shibata
发明人： Fumitoshi Kawase , Satoshi Shibata
IPC分类号： A61N5/00 , C23C16/00 , H01L21/324
CPC分类号： H01L21/324 , H01L21/67109 , H01L21/67115 , H01L27/10894 , H01L29/665 , Y10S438/914
摘要： In this invention, a wafer is placed and kept in the low-temperature region at the bottom of a temperature space that is in a state of radiation equilibrium and that is formed inside chamber by a heating unit. The substrate temperature is gradually raised to 750 deg C. to 800 deg C. Next, the wafer is placed and kept in the high-temperature region in the temperature space and the substrate temperature is raised to the thermal processing temperature. Then thermal processing is performed for a specified period of time. By doing this, it is possible to perform uniform thermal processing without depending on the state of the wafer (ratio of an area covered by silicon nitride film or polysilicon film).
摘要翻译： 在本发明中，将晶片放置并保持在处于辐射平衡状态的温度空间的底部的低温区域，并且通过加热单元形成在室内。 将衬底温度逐渐升高至750摄氏度至800摄氏度。接下来，将晶片放置并保持在温度空间中的高温区域中，并将衬底温度升高至热处理温度。 然后进行热处理一段规定的时间。 通过这样做，可以不依赖于晶片的状态（氮化硅膜或多晶硅膜覆盖的区域的比例）进行均匀的热处理。
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公开(公告)号：US08088632B2
公开(公告)日：2012-01-03
申请号：US12494977
申请日：2009-06-30
IPC分类号： H01L21/00
CPC分类号： H01L22/20 , H01J2237/2566 , H01J2237/31703 , H01L22/12
摘要： Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present in the substrate to be analyzed are identified based on the measured characteristic X-ray. The in-plane distribution in the substrate can be obtained by scanning the proton beam. The in-depth distribution can be obtained by entering protons at different proton incident angles. The elemental analysis method can be applied to semiconductor device manufacturing processes to analyze metal contamination or quantify a conductivity determining impurity element on an inline basis and with a high degree of accuracy.
摘要翻译： 质子以大于0°和较小90°的质子入射角进入基底进行分析。 由输入的质子激发并从要分析的基板发射，通过能量色散X射线检测器等测量特征X射线。 基于所测量的特征X射线识别存在于待分析基板中的杂质元素。 可以通过扫描质子束来获得衬底中的面内分布。 可以通过在不同的质子入射角进入质子来获得深度分布。 元素分析方法可以应用于半导体器件制造工艺，以分析金属污染或者在线性基础上以高准确度量化电导率确定杂质元素。
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9.发明授权Method for measuring temperature, annealing method and method for fabricating semiconductor device 有权测量温度的方法，退火方法和制造半导体器件的方法公开(公告)号：US07037733B2
公开(公告)日：2006-05-02
申请号：US10343762
申请日：2002-07-01
申请人： Satoshi Shibata , Junji Hirase , Tatsuo Sugiyama , Emi Kanasaki , Fumitoshi Kawase , Yasushi Naito
发明人： Satoshi Shibata , Junji Hirase , Tatsuo Sugiyama , Emi Kanasaki , Fumitoshi Kawase , Yasushi Naito
CPC分类号： G01J5/0003
摘要： When the emissivity ε on the reverse face of a substrate 10 is measured during annealing processing for the substrate 10, films made from a material that varies the emissivity ε, such as a first DPS film 15 used for forming a plug 15A, a second DPS film 17 used for forming a capacitor lower electrode 17A and a third DPS film 20 used for forming a capacitor upper electrode 20A, are formed on the top face of the substrate 10. On the other hand, no film made from a material that varies the emissivity ε, such as a DPS film, is formed on the reverse face of the substrate 10.
摘要翻译： 当在衬底10的退火处理期间测量衬底10的反面上的发射率ε时，由用于形成插头15A的第一DPS膜15，例如用于形成插头15A的第一DPS膜15的材料制成的膜，第二 用于形成用于形成电容器上电极20A的电容器下电极17A和第三DPS膜20的DPS膜17形成在基板10的顶面上。另一方面，没有由材料制成的膜 在基板10的背面上形成改变发射率ε（例如DPS膜）。
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10.发明授权Method for thermal processing with a RTP process using temperature spaces in radiation equilibrium 失效使用辐射平衡中温度空间的RTP工艺进行热处理的方法公开(公告)号：US07560367B2
公开(公告)日：2009-07-14
申请号：US11353145
申请日：2006-02-14
申请人： Fumitoshi Kawase , Satoshi Shibata
发明人： Fumitoshi Kawase , Satoshi Shibata
IPC分类号： H01L21/425
CPC分类号： H01L21/324 , H01L21/67109 , H01L21/67115 , H01L27/10894 , H01L29/665 , Y10S438/914
摘要： In this invention, a wafer is placed and kept in the low-temperature region at the bottom of a temperature space that is in a state of radiation equilibrium and that is formed inside chamber by a heating unit. The substrate temperature is gradually raised to a temperature ranging from 750° C. to 800° C. Next, the wafer is placed and kept in the high-temperature region in the temperature space and the substrate temperature is raised to the thermal processing temperature. Then thermal processing is performed for a specified period of time. By doing this, it is possible to perform uniform thermal processing without depending on the state of the wafer (ratio of an area covered by silicon nitride film or polysilicon film).
摘要翻译： 在本发明中，将晶片放置并保持在处于辐射平衡状态的温度空间的底部的低温区域，并且通过加热单元形成在室内。 将衬底温度逐渐升至750℃至800℃的温度。接下来，将晶片放置并保持在温度空间的高温区域中，并将衬底温度升高至热处理温度。 然后进行热处理一段规定的时间。 通过这样做，可以不依赖于晶片的状态（氮化硅膜或多晶硅膜覆盖的区域的比例）进行均匀的热处理。
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