公开(公告)号：US08587076B2

公开(公告)日：2013-11-19

申请号：US13547913

申请日：2012-07-12

申请人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

发明人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L27/108 ,  H01L31/119 ,  H01L31/062

CPC分类号： H01L29/4983 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

摘要翻译： 半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。 高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。 位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

公开(公告)号：US08253180B2

公开(公告)日：2012-08-28

申请号：US13037831

申请日：2011-03-01

申请人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

发明人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4983 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

摘要翻译： 半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。 高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。 位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

公开(公告)号：US20110147857A1

公开(公告)日：2011-06-23

申请号：US13037831

申请日：2011-03-01

申请人： Junji HIRASE ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

发明人： Junji HIRASE ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

IPC分类号： H01L29/772

CPC分类号： H01L29/4983 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

摘要翻译： 半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。 高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。 位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

公开(公告)号：US07732839B2

公开(公告)日：2010-06-08

申请号：US11525011

申请日：2006-09-22

申请人： Akio Sebe ,  Naoki Kotani ,  Shinji Takeoka ,  Gen Okazaki ,  Junji Hirase ,  Kazuhiko Aida

发明人： Akio Sebe ,  Naoki Kotani ,  Shinji Takeoka ,  Gen Okazaki ,  Junji Hirase ,  Kazuhiko Aida

IPC分类号： H01L27/10

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A MIS transistor includes a gate electrode portion, insulating sidewalls formed on side surfaces of the gate electrode portion, source/drain regions and a stress film formed so as to cover the gate electrode portion and the source/drain regions. A height of an upper surface of the gate electrode portion is smaller than a height of an upper edge of each of the insulating sidewalls. A thickness of first part of the stress film located on the gate electrode portion is larger than a thickness of second part of the stress film located on the source/drain regions.

摘要翻译： MIS晶体管包括栅电极部分，形成在栅电极部分的侧表面上的绝缘侧壁，源极/漏极区域和形成为覆盖栅电极部分和源极/漏极区域的应力膜。 栅电极部分的上表面的高度小于每个绝缘侧壁的上边缘的高度。 位于栅电极部分的应力膜的第一部分的厚度大于位于源/漏区上的应力膜的第二部分的厚度。

公开(公告)号：US06066522A

公开(公告)日：2000-05-23

申请号：US923134

申请日：1997-09-04

申请人： Junji Hirase

发明人： Junji Hirase

IPC分类号： H01L21/8238 ,  H01L21/74 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/105 ,  H01L21/74 ,  H01L21/823892 ,  H01L27/0922

摘要： A semiconductor device include: a substrate of a conductivity type; a first well provided in the substrate and of the same conductivity type as the conductivity type of the substrate; a second well provided in the substrate and of an opposite conductivity type to the conductivity type of the substrate; and a buried well provided at a deep position in the substrate and of the opposite conductivity type to the conductivity type of the substrate. A buried well of the same conductivity type as the conductivity type of the substrate is further provided so as to be in contact with at least a part of a bottom portion of the first well so that the first well is at least partially electrically connected to the substrate.

摘要翻译： 半导体器件包括：导电类型的衬底; 设置在基板中并且与基板的导电类型相同的导电类型的第一阱; 第二阱，设置在衬底中并且与衬底的导电类型相反的导电类型; 以及设置在衬底中的深位置并且与衬底的导电类型相反的导电类型的埋置阱。 进一步提供与基板的导电类型相同的导电类型的掩埋阱，以便与第一阱的底部的至少一部分接触，使得第一阱至少部分地电连接到 基质。

公开(公告)号：US5672995A

公开(公告)日：1997-09-30

申请号：US340343

申请日：1994-11-14

申请人： Junji Hirase ,  Hironori Akamatsu ,  Susumu Akamatsu ,  Takashi Hori

发明人： Junji Hirase ,  Hironori Akamatsu ,  Susumu Akamatsu ,  Takashi Hori

IPC分类号： H01L27/04 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/108 ,  H01J19/82 ,  G05F1/10

CPC分类号： H01L27/0218

摘要： There are provided a MIS transistor having a substrate portion, a gate, a source, and a drain, a back-bias generator to be applied to the substrate portion of the MIS transistor, and a resistor interposed between the substrate portion of the MIS transistor and the back-bias generator so that the potential between the both ends thereof changes in a range from one value in the active mode to the other value in the standby mode of the MIS transistor. In the MIS transistor, the back bias is self-regulated so that it approaches to zero in the active mode, while it moves away from zero in the standby mode. Consequently, the threshold voltage is reduced in the active mode due to the back bias approaching to zero, so that higher-speed operation is performed. On the other hand, off-state leakage is suppressed in the standby mode due to the back bias moving away from zero. Thus, it becomes possible to constitute a semiconductor apparatus which operates at high speed with low power consumption.

摘要翻译： 提供了具有衬底部分，栅极，源极和漏极的MIS晶体管，施加到MIS晶体管的衬底部分的反向偏置发生器，以及插入在MIS晶体管的衬底部分之间的电阻器 和偏压发生器，使得其两端之间的电位在从动模式中的一个值到MIS晶体管的待机模式中的另一个值的范围内变化。 在MIS晶体管中，背偏压是自调节的，使得它在有功模式下接近零，而在待机模式下它偏离零。 因此，由于反向偏压接近零，所以在激活模式中阈值电压降低，从而执行更高速度的操作。 另一方面，由于背偏压偏离零，在待机模式下，截止状态泄漏被抑制。 因此，可以构成以低功耗高速运转的半导体装置。

公开(公告)号：US5468983A

公开(公告)日：1995-11-21

申请号：US203627

申请日：1994-03-01

申请人： Junji Hirase ,  Shin Hashimoto

发明人： Junji Hirase ,  Shin Hashimoto

IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  H01L33/00

CPC分类号： H01L27/108 ,  H01L27/105

摘要： In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region. At last one of dummy cells is made to be a P-N lacking dummy cell having a semiconductor element in construction including at least a gate and excluding at least one of P-N junction parts from the same construction as the field effect semiconductor element in the active cells. All dummy cells may be the P-N lacking dummy cells. Thereby, insulation defects through the P-N lacking dummy cell due to disturbance of gate pattern and the like in the dummy cell region is prevented.

摘要翻译： 在半导体器件中，由绝缘部分隔开的集成电路区域的外周部分被定义为虚设单元区域，并且除了集成电路区域的外周部分之外的中心部分被定义为有源单元区域。 诸如DRAM，SRAM，EEPROM，掩模ROM的存储单元形成在活动单元区域中。 在集成电路区域中，设置多个单元形成区，分别由隔离限定。 每个具有场效应半导体元件的有源电池被提供在每个电池形成区域的有源电池区域中包括的区域中。 每个具有不可用作半导体元件的元件的虚拟单元设置在每个单元形成区域的虚拟单元区域中包括的区域中。 最后一个虚设单元被制成为具有至少具有栅极并且从与活性单元中的场效应半导体元件相同结构的P-N结部分中的至少一个排列的至少一个半导体元件的P-N缺乏的虚设单元。 所有虚拟细胞可能是缺乏伪细胞的P-N。 因此，防止了由于虚设单元区域中的栅极图案等的干扰而导致的缺乏虚设单元的P-N的绝缘缺陷。

公开(公告)号：US20090189225A1

公开(公告)日：2009-07-30

申请号：US12357869

申请日：2009-01-22

申请人： Junji HIRASE

发明人： Junji HIRASE

IPC分类号： H01L21/336 ,  H01L27/092

CPC分类号： H01L21/82345 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/517 ,  Y10S257/901

摘要： A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The first MIS transistor includes a first gate insulating film made of a high-k insulating film formed on a first channel region, and a first gate electrode having a first conductive portion provided on and contacting the first gate insulating film and a second conductive portion. The second MIS transistor includes a second gate insulating film made of the high-k insulating film formed on a second channel region, and a second gate electrode having a third conductive portion provided on and contacting the second gate insulating film and a fourth conductive portion. The third conductive portion has a film thickness smaller than that of the first conductive portion, and is made of the same composition material as that of the first conductive portion.

摘要翻译： 半导体器件包括第一MIS晶体管和具有高于第一MIS晶体管的阈值电压的阈值电压的第二MIS晶体管。 第一MIS晶体管包括由形成在第一沟道区上的高k绝缘膜制成的第一栅极绝缘膜和具有设置在第一栅极绝缘膜上并与第一栅极绝缘膜接触的第一导电部分的第一栅电极和第二导电部分。 第二MIS晶体管包括由形成在第二沟道区上的高k绝缘膜制成的第二栅极绝缘膜和具有设置在第二栅极绝缘膜上并与第二栅极绝缘膜接触的第三导电部分的第二栅电极和第四导电部分。 第三导电部分的膜厚度小于第一导电部分的厚度，并且由与第一导电部分相同的组成材料制成。

公开(公告)号：US07495299B2

公开(公告)日：2009-02-24

申请号：US11544611

申请日：2006-10-10

申请人： Kazuhiko Aida ,  Junji Hirase ,  Hisashi Ogawa ,  Chiaki Kudo

发明人： Kazuhiko Aida ,  Junji Hirase ,  Hisashi Ogawa ,  Chiaki Kudo

IPC分类号： H01L29/78

CPC分类号： H01L21/82345 ,  H01L21/823437 ,  H01L21/823443 ,  H01L27/0207 ,  H01L29/665

摘要： The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebetween and forming another dummy gate electrode on the semiconductor substrate with an insulating film for isolation interposed therebetween; forming a metal film on the semiconductor while exposing the gate electrode and covering the dummy gate electrodes; and subjecting the semiconductor substrate to heat treatment and thus siliciding at least an upper part of the gate electrode. Since the gate electrode is silicided and the dummy gate electrodes are non-silicided, this restrains a short circuit from being caused between the gate electrode and adjacent one of the dummy gate electrodes.

摘要翻译： 执行以下步骤：在半导体衬底上形成栅电极，其间插入栅极绝缘膜，在半导体衬底上形成具有虚拟栅绝缘膜的虚拟栅电极，并在半导体衬底上形成另一虚拟栅电极 其间插入有用于隔离的绝缘膜; 在半导体上形成金属膜，同时露出栅电极并覆盖伪栅电极; 对半导体基板进行热处理，至少使栅电极的上部被硅化。 由于栅电极是硅化的，并且虚拟栅电极是非硅化的，所以这抑制了在栅电极和相邻的一个虚拟栅电极之间的短路。

公开(公告)号：US20080258229A1

公开(公告)日：2008-10-23

申请号：US12028392

申请日：2008-02-08

申请人： Hiroshi OHKAWA ,  Junji Hirase ,  Hisashi Ogawa ,  Kenji Yoneda

发明人： Hiroshi OHKAWA ,  Junji Hirase ,  Hisashi Ogawa ,  Kenji Yoneda

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/518

摘要： A semiconductor device includes an N-type MOS transistor and a P-type MOS transistor. The N-type MOS transistor has a first gate insulating film and a first gate electrode. The P-type MOS transistor has a second gate insulating film and a second gate electrode. The first gate insulating film and the second gate insulating film are made of silicon oxynitride, and the first gate insulating film and the second gate insulating film are different from each other in nitrogen concentration profile.

摘要翻译： 半导体器件包括N型MOS晶体管和P型MOS晶体管。 N型MOS晶体管具有第一栅极绝缘膜和第一栅极电极。 P型MOS晶体管具有第二栅极绝缘膜和第二栅极电极。 第一栅极绝缘膜和第二栅极绝缘膜由氮氧化硅制成，并且第一栅极绝缘膜和第二栅极绝缘膜在氮浓度分布中彼此不同。