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公开(公告)号：US20060035459A1
公开(公告)日：2006-02-16
申请号：US10916167
申请日：2004-08-11
申请人： Emmanuil Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
发明人： Emmanuil Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L27/11568 , G03F1/36 , H01L27/115 , Y10S438/942 , Y10S438/947
摘要： A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.
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2.发明授权Method of forming narrowly spaced flash memory contact openings and lithography masks 有权形成窄间隔闪存接触开口和光刻掩模的方法公开(公告)号：US07507661B2
公开(公告)日：2009-03-24
申请号：US10916167
申请日：2004-08-11
申请人： Emmanuil H. Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
发明人： Emmanuil H. Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
IPC分类号： H01L21/44
CPC分类号： H01L27/11568 , G03F1/36 , H01L27/115 , Y10S438/942 , Y10S438/947
摘要： A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.
摘要翻译： 提供了一种用于在光刻掩模上产生光学特征的方法，用于在半导体器件晶片上图案化一系列蚀刻掩模的开口，包括沿着第一方向在光刻掩模上彼此间隔开的一系列光学特征， 其中各个光学特征具有沿着第一方向的第一掩模特征尺寸，其小于用于在蚀刻掩模中图案化的开口的期望的第一尺寸。
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公开(公告)号：US20050221233A1
公开(公告)日：2005-10-06
申请号：US10817193
申请日：2004-04-02
申请人： Anna Minvielle , Cyrus Tabery , Hung-eil Kim , Jongwook Kye
发明人： Anna Minvielle , Cyrus Tabery , Hung-eil Kim , Jongwook Kye
CPC分类号： G03F7/70425 , G03F7/70091 , G03F7/701 , G03F7/70125 , G03F7/70158
摘要： A method of forming a plurality of contact holes of varying pitch and density in a contact layer of an integrated circuit device is provided. The plurality of contact holes can include a plurality of regularly spaced contact holes having a first pitch along a first direction and a plurality of semi-isolated contact holes having a second pitch along a second direction. A double-dipole illumination source can transmit light energy through a mask having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source can include a first dipole aperture, which is oriented and optimized for patterning the regularly spaced contact holes, and a second dipole aperture, which is oriented substantially orthogonal to the first dipole aperture and optimized for patterning the plurality of semi-isolated contact holes. The contact layer can be etched using the patterned photoresist layer.
摘要翻译： 提供了一种在集成电路器件的接触层中形成多个具有不同间距和密度的接触孔的方法。 多个接触孔可以包括沿着第一方向具有第一间距的多个规则间隔的接触孔和沿第二方向具有第二间距的多个半隔离接触孔。 双偶极照明源可以通过具有对应于期望的接触孔图案的图案的掩模传输光能。 双偶极照明源可以包括第一偶极孔，其被定向和优化以用于图案化规则间隔的接触孔，以及第二偶极孔，其基本上垂直于第一偶极孔定向并且被优化用于图案化多个半 隔离接触孔。 可以使用图案化的光致抗蚀剂层来蚀刻接触层。
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公开(公告)号：US06900124B1
公开(公告)日：2005-05-31
申请号：US10654739
申请日：2003-09-03
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译： 公开了一种在闪速存储器件中形成触点的方法。 该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。 在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。 层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。 接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。 导电层沉积在接触孔中，去除过量的导电材料。
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公开(公告)号：US07018922B1
公开(公告)日：2006-03-28
申请号：US10968713
申请日：2004-10-19
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译： 公开了一种在闪速存储器件中形成触点的方法。 该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。 在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。 层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。 接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。 导电层沉积在接触孔中，去除过量的导电材料。
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6.发明授权Utilizing electrical performance data to predict CD variations across stepper field 失效利用电气性能数据来预测跨步域的CD变化公开(公告)号：US06562639B1
公开(公告)日：2003-05-13
申请号：US09993166
申请日：2001-11-06
IPC分类号： H01L2166
CPC分类号： G03F7/70625 , G03F7/70658 , H01L22/34
摘要： In order to determine an amount of critical dimension variation to expect across a surface of a final production wafer, a plurality of test structures are formed on a test wafer. The test structures are preferably of a type commonly found on the final production wafer and may for example, include transistors, ring oscillators, resistors and/or diodes. Electrical parameter testing of the test structures is next conducted in order to obtain one or more electrical performance values for each test structure. For example, the electrical performance values may correspond to processing speed, drive current, and/or off-state current of the test structures. A correlation between the electrical performance values and expected critical dimension variations is then performed and a report is generated providing the expected critical dimension variations across the surface of the wafer. Expected critical dimension variations may be accounted for by varying characteristics of devices used during a photolithographic transfer process to the final production wafers.
摘要翻译： 为了确定在最终生产晶片的表面上期望的临界尺寸变化的量，在测试晶片上形成多个测试结构。 测试结构优选地是在最终生产晶片上常见的类型，并且可以例如包括晶体管，环形振荡器，电阻器和/或二极管。 接下来进行测试结构的电气参数测试，以获得每个测试结构的一个或多个电性能值。 例如，电性能值可对应于测试结构的处理速度，驱动电流和/或截止状态电流。 然后执行电性能值和预期临界尺寸变化之间的相关性，并且生成提供晶片表面上的预期临界尺寸变化的报告。 预期的临界尺寸变化可以通过将光刻转印过程中使用的器件的特性改变到最终生产晶片来考虑。
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7.发明授权Negative resist or dry develop process for forming middle of line implant layer 有权用于形成线植入层中间的负阻抗或干式显影工艺公开(公告)号：US07112489B1
公开(公告)日：2006-09-26
申请号：US11004691
申请日：2004-12-03
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/115 , H01L21/26513 , H01L27/11521
摘要： A method of implanting a middle of line (MOL) implant layer of a flash memory device that does not require a descumming step is disclosed. In a first embodiment, the method includes depositing a negative tone resist over the MOL implant layer. Portions of the negative tone resist in and above a plurality of trenches are not exposed to optical radiation, while portions surrounding the plurality of trenches are exposed. The unexposed portions are developed out thereby leaving a bottom surface of each trench substantially free of a resist residue. Implants can be placed in the MOL implant layer without the need for a descumming step. In a second embodiment, a bi-layer resist is deposited on the MOL implant layer, wherein the bi-layer resist includes a silicon containing top layer and a bottom layer. The bi-layer resist is patterned to expose a portion of the bottom layer that resides in and above a plurality of trenches. The bottom layer is dry etch developed using oxygen plasma as the etchant, thereby leaving a bottom surface of each trench substantially free of a resist residue. Implants can be placed in the MOL implant layer without the need for a descumming step.
摘要翻译： 公开了一种注入不需要除尘步骤的闪速存储器件的中间线（MOL）注入层的方法。 在第一实施例中，该方法包括在MOL植入层上沉积负色调抗蚀剂。 在多个沟槽中和上方的负色调抗蚀剂的部分不暴露于光辐射，而围绕多个沟槽的部分被暴露。 未曝光部分显影出来，从而留下每个沟槽的底表面基本上没有抗蚀剂残留物。 植入物可以放置在MOL植入层中，而不需要除去步骤。 在第二实施例中，双层抗蚀剂沉积在MOL注入层上，其中双层抗蚀剂包括含硅顶层和底层。 图案化双层抗蚀剂以暴露驻留在多个沟槽中和上方的底层的一部分。 底层是使用氧等离子体作为蚀刻剂进行干法蚀刻，从而留下每个沟槽的底表面基本上没有抗蚀剂残留物。 植入物可以放置在MOL植入层中，而不需要除去步骤。
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公开(公告)号：US5963816A
公开(公告)日：1999-10-05
申请号：US982072
申请日：1997-12-01
申请人： Larry Yu Wang , Craig Sander , Anna Minvielle
发明人： Larry Yu Wang , Craig Sander , Anna Minvielle
IPC分类号： H01L21/762 , H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L21/76224 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002
摘要： The separate formation of alignment marks and manufacturing a semiconductor device comprising photolithographically printing circuit patterns is avoided by utilizing trenches formed when etching to form shallow isolation trenches, thereby increasing manufacturing throughput and reducing costs. Embodiments include utilizing alignment trenches having a depth of about 2,400.ANG. to less than about 4,000.ANG., e.g., 3,000.ANG., formed substantially simultaneously with forming isolation trenches having substantially the same depth as the alignment trenches.
摘要翻译： 通过利用在蚀刻时形成的沟槽形成浅隔离沟槽，从而避免了制造包括光刻印刷电路图形的半导体器件的单独形成，从而提高了制造量并降低了成本。 实施例包括使用具有大约2,400安培的深度的对准沟槽，以小于约4,000安培，例如3,000安培，其基本上同时形成，形成具有与对准沟槽基本相同的深度的隔离沟槽。
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