公开(公告)号：US08510699B1

公开(公告)日：2013-08-13

申请号：US13416588

申请日：2012-03-09

申请人： Emrah Acar ,  Aditya Bansal ,  Rama N. Singh ,  Amith Singhee

发明人： Emrah Acar ,  Aditya Bansal ,  Rama N. Singh ,  Amith Singhee

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F9/455 ,  G06F17/5068

摘要： Techniques for generating variants of a circuit layout and evaluating quality of the variants are provided. In one aspect, a method for generating at least one variant layout for a cell design includes the following steps. At least a first basis layout and a second basis layout are obtained for the cell design, each having a plurality of shapes, each of the shapes being a polygon having a plurality of sides and vertices. One or more of the shapes in the first basis layout are linked with one or more of the shapes in the second basis layout that represent a common feature of the cell design resulting in a plurality of linked shapes. Starting with either the first basis layout or the second basis layout, a location of the vertices of each of the linked shapes are changed to produce the variant layout for the cell design.

摘要翻译： 提供了用于产生电路布局的变型和评估变体的质量的技术。 一方面，用于为单元设计生成至少一个变体布局的方法包括以下步骤。 为单元设计获得至少第一基础布局和第二基本布局，每个布局具有多个形状，每个形状是具有多个边和顶点的多边形。 第一基本布局​​中的一个或多个形状与第二基本布局中的一个或多个形状相关联，其表示单元设计的共同特征，导致多个连接形状。 从第一基本布局​​或第二基本布局开始，改变每个链接形状的顶点的位置，以产生单元格设计的变体布局。

公开(公告)号：US20130320340A1

公开(公告)日：2013-12-05

申请号：US13488532

申请日：2012-06-05

申请人： Emrah Acar ,  Aditya Bansal ,  Dureseti Chidambarrao ,  Liang-Teck Pang ,  Amith Singhee

发明人： Emrah Acar ,  Aditya Bansal ,  Dureseti Chidambarrao ,  Liang-Teck Pang ,  Amith Singhee

IPC分类号： H01L21/66 ,  H01L23/50

CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L27/0203 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

摘要： A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

公开(公告)号：US08969104B2

公开(公告)日：2015-03-03

申请号：US13488532

申请日：2012-06-05

申请人： Emrah Acar ,  Aditya Bansal ,  Dureseti Chidambarrao ,  Liang-Teck Pang ,  Amith Singhee

发明人： Emrah Acar ,  Aditya Bansal ,  Dureseti Chidambarrao ,  Liang-Teck Pang ,  Amith Singhee

IPC分类号： H01L23/34

CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L27/0203 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

摘要： A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

摘要翻译： 物理测试集成电路具有对应于集成电路设计的多个重复电路部分。 这些部分中的第一部分被制造成具有标称块掩模位置，并且附加的部分被有意地用块掩模位置与标称块掩模位置的预定逐渐增加的偏移来制造。 对于每个部分，确定第一场效应晶体管和第二场效应晶体管之间的阈值电压差。 块掩模位置的预定逐渐增加的偏移在从第一场效应晶体管到第二场效应晶体管的方向上。 在与零差异的阈值电压的差的变化相对应的逐行增加偏移的值处确定块掩模覆盖公差。 还公开了用于片上监视的方法和相应的电路。

公开(公告)号：US20110115463A1

公开(公告)日：2011-05-19

申请号：US12617901

申请日：2009-11-13

申请人： Emrah Acar ,  Aditya Bansal ,  Amith Singhee

发明人： Emrah Acar ,  Aditya Bansal ,  Amith Singhee

IPC分类号： G01N27/00

CPC分类号： G03F7/70633 ,  H01L22/34

摘要： A method and apparatus for determining overlay includes an array of electronic devices having structures formed in a plurality of layers and such that a device on a first end of the array includes an offset from a position of a device on a second end of the array. A measurement device is configured to measure electrical characteristics of the devices in the array to determine a transition position between the electrical characteristics. A comparison device is configured to determine an overlay between the layers based on a device associated with the transition position.

摘要翻译： 用于确定覆盖层的方法和装置包括具有形成在多个层中的结构的电子器件的阵列，并且使得阵列的第一端上的器件包括从阵列的第二端上的器件的位置的偏移。 测量装置被配置为测量阵列中的装置的电特性以确定电特性之间的转变位置。 比较设备被配置为基于与转换位置相关联的设备来确定层之间的覆盖。

公开(公告)号：US08409882B2

公开(公告)日：2013-04-02

申请号：US12617901

申请日：2009-11-13

申请人： Emrah Acar ,  Aditya Bansal ,  Amith Singhee

发明人： Emrah Acar ,  Aditya Bansal ,  Amith Singhee

IPC分类号： H01L21/66

CPC分类号： G03F7/70633 ,  H01L22/34

摘要： A method and apparatus for determining overlay includes an array of electronic devices having structures formed in a plurality of layers and such that a device on a first end of the array includes an offset from a position of a device on a second end of the array. A measurement device is configured to measure electrical characteristics of the devices in the array to determine a transition position between the electrical characteristics. A comparison device is configured to determine an overlay between the layers based on a device associated with the transition position.

摘要翻译： 用于确定覆盖层的方法和装置包括具有形成在多个层中的结构的电子器件的阵列，并且使得阵列的第一端上的器件包括从阵列的第二端上的器件的位置的偏移。 测量装置被配置为测量阵列中的装置的电特性以确定电特性之间的转变位置。 比较设备被配置为基于与转换位置相关联的设备来确定层之间的覆盖。

公开(公告)号：US20110172979A1

公开(公告)日：2011-07-14

申请号：US12685108

申请日：2010-01-11

申请人： Aditya Bansal ,  Pamela Castalino ,  Dallas M. Lea ,  Amith Singhee

发明人： Aditya Bansal ,  Pamela Castalino ,  Dallas M. Lea ,  Amith Singhee

IPC分类号： G06G7/48

CPC分类号： G06F17/5022 ,  G06F17/5036

摘要： A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values.

摘要翻译： 公开了一种用于评估模型的方法，其特征在于是计算机可执行装置和电路模拟器。 该方法包括接收设备的测量参数，哪些设备基本上与模拟电路实例相同或实际来自模拟电路实例。 该模型通过调整的输入参数执行，以生成电路实例属性的模拟值。 将这些模拟值与相同属性的测量值进行比较。 模型的好处是基于模拟值和测量值之间的直接或统计一致程度来确定的。

公开(公告)号：US08606556B2

公开(公告)日：2013-12-10

申请号：US12685108

申请日：2010-01-11

申请人： Aditya Bansal ,  Pamela Castalino ,  Dallas M. Lea ,  Amith Singhee

发明人： Aditya Bansal ,  Pamela Castalino ,  Dallas M. Lea ,  Amith Singhee

IPC分类号： G06F17/50 ,  G06G7/62

CPC分类号： G06F17/5022 ,  G06F17/5036

摘要： A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values.

摘要翻译： 公开了一种用于评估模型的方法，其特征在于是计算机可执行装置和电路模拟器。 该方法包括接收设备的测量参数，哪些设备基本上与模拟电路实例相同或实际来自模拟电路实例。 该模型通过调整的输入参数执行，以生成电路实例属性的模拟值。 将这些模拟值与相同属性的测量值进行比较。 模型的好处是基于模拟值和测量值之间的直接或统计一致程度来确定的。

公开(公告)号：US08407632B2

公开(公告)日：2013-03-26

申请号：US12881548

申请日：2010-09-14

申请人： Ibrahim M. Elfadel ,  Ying Liu ,  Stanislav Polonsky ,  Amith Singhee

发明人： Ibrahim M. Elfadel ,  Ying Liu ,  Stanislav Polonsky ,  Amith Singhee

IPC分类号： G06F17/50

CPC分类号： G03F7/705 ,  G03F7/70658

摘要： A method, system, and computer usable program product for detecting dose and focus variations during photolithography are provided in the illustrative embodiments. A test shape is formed on a wafer, the wafer being used to manufacture integrated circuits, the test shape being formed using a dose value and a focus value that are predetermined for the manufacturing. A capacitance of the test shape is measured. The capacitance is resolved to a second dosing value and a second focus value using an extraction model. A difference between the dosing value and the second dosing value is computed. A recommendation is made for dosing adjustment in the manufacturing based on the difference.

摘要翻译： 在说明性实施例中提供了用于在光刻期间检测剂量和聚焦变化的方法，系统和计算机可用程序产品。 在晶片上形成测试形状，该晶片用于制造集成电路，该测试形状使用为制造预定的剂量值和聚焦值形成。 测量测试形状的电容。 使用提取模型将电容解析为第二计量值和第二焦点值。 计算给药值和第二给药值之间的差异。 基于差异，建议制造中的剂量调整。

公开(公告)号：US20110307430A1

公开(公告)日：2011-12-15

申请号：US12814043

申请日：2010-06-11

申请人： Amith Singhee

发明人： Amith Singhee

IPC分类号： G06N3/12 ,  G06N5/02

CPC分类号： G06F17/11

摘要： A method of optimizing a plurality of objectives includes the steps of initializing a set of simplices; selecting a simplex from the set of simplices; computing one or more weights based at least in part on the selected simplex; and generating a point on a tradeoff surface by utilizing the one or more weights in a weighted-sum optimization.

摘要翻译： 优化多个目标的方法包括初始化一组简单的步骤; 从一组单纯形中选择一个单纯形; 至少部分地基于所选择的单项计算一个或多个权重; 以及通过在加权和优化中利用所述一个或多个权重来在权衡表面上生成点。

公开(公告)号：US20090248370A1

公开(公告)日：2009-10-01

申请号：US12057260

申请日：2008-03-27

申请人： Rob Rutenbar ,  Amith Singhee

发明人： Rob Rutenbar ,  Amith Singhee

IPC分类号： G06F17/50 ,  G06F17/11

CPC分类号： G06F17/5036 ,  G06F2217/10

摘要： The invention discloses a “Quasi-Monte Carlo” method originally intended for computational finance applications and applies said method to statistical circuit analysis. In doing so, it provides a means to efficiently and effectively detect and/or predict relatively rare failures or events to a wide range of industrial circuits and systems. The approach to the invention involves the representation of circuit metrics as a large multi-dimensional integral. This invention estimates such statistical circuit metric integrals by sampling the statistical variable space using a so-called “low-discrepancy sequence.” This is similar to the Monte Carlo method, the main difference being the method of sampling the variable space. Compared with standard Monte Carlo simulation, this technique, “Quasi-Monte Carlo Methods,” gives similarly reliable estimates of the result, but requiring many fewer samples of the circuit or system being evaluated. In practice, speedups of 2× to 50× across a range of practical examples are observed.

摘要翻译： 本发明公开了一种原拟用于计算金融应用的“准蒙特卡罗”方法，并将所述方法应用于统计电路分析。 在这样做时，它提供了一种手段，能够有效和高效地检测和/或预测各种工业电路和系统的相对罕见的故障或事件。 本发明的方法涉及将电路量度表示为大的多维积分。 本发明通过使用所谓的“低差异序列”对统计变量空间进行采样来估计这种统计电路量度积分。 这与蒙特卡罗方法类似，主要区别在于对可变空间进行抽样的方法。 与标准蒙特卡罗模拟相比，该技术“准蒙特卡罗方法”给出了相当可靠的结果估计，但是要评估的电路或系统的样本数量要少得多。 实际上，观察到在一系列实际例子中加速了2x至50x。