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    Circuit technique to electrically characterize block mask shifts
    2.
    发明授权
    Circuit technique to electrically characterize block mask shifts 有权
    电路技术，用于表征块掩模移位

    公开(公告)号：US08969104B2

    公开(公告)日：2015-03-03

    申请号：US13488532

    申请日：2012-06-05

    申请人： Emrah Acar ,  Aditya Bansal ,  Dureseti Chidambarrao ,  Liang-Teck Pang ,  Amith Singhee

    发明人： Emrah Acar ,  Aditya Bansal ,  Dureseti Chidambarrao ,  Liang-Teck Pang ,  Amith Singhee

    IPC分类号： H01L23/34

    CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L27/0203 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

    摘要翻译： 物理测试集成电路具有对应于集成电路设计的多个重复电路部分。 这些部分中的第一部分被制造成具有标称块掩模位置，并且附加的部分被有意地用块掩模位置与标称块掩模位置的预定逐渐增加的偏移来制造。 对于每个部分，确定第一场效应晶体管和第二场效应晶体管之间的阈值电压差。 块掩模位置的预定逐渐增加的偏移在从第一场效应晶体管到第二场效应晶体管的方向上。 在与零差异的阈值电压的差的变化相对应的逐行增加偏移的值处确定块掩模覆盖公差。 还公开了用于片上监视的方法和相应的电路。

    Performance driven layout optimization using morphing of a basis set of representative layouts
    3.
    发明授权
    Performance driven layout optimization using morphing of a basis set of representative layouts 失效
    性能驱动布局优化使用变形的基础代表性布局

    公开(公告)号：US08510699B1

    公开(公告)日：2013-08-13

    申请号：US13416588

    申请日：2012-03-09

    申请人： Emrah Acar ,  Aditya Bansal ,  Rama N. Singh ,  Amith Singhee

    发明人： Emrah Acar ,  Aditya Bansal ,  Rama N. Singh ,  Amith Singhee

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F9/455 ,  G06F17/5068

    摘要： Techniques for generating variants of a circuit layout and evaluating quality of the variants are provided. In one aspect, a method for generating at least one variant layout for a cell design includes the following steps. At least a first basis layout and a second basis layout are obtained for the cell design, each having a plurality of shapes, each of the shapes being a polygon having a plurality of sides and vertices. One or more of the shapes in the first basis layout are linked with one or more of the shapes in the second basis layout that represent a common feature of the cell design resulting in a plurality of linked shapes. Starting with either the first basis layout or the second basis layout, a location of the vertices of each of the linked shapes are changed to produce the variant layout for the cell design.

    摘要翻译： 提供了用于产生电路布局的变型和评估变体的质量的技术。 一方面，用于为单元设计生成至少一个变体布局的方法包括以下步骤。 为单元设计获得至少第一基础布局和第二基本布局，每个布局具有多个形状，每个形状是具有多个边和顶点的多边形。 第一基本布局​​中的一个或多个形状与第二基本布局中的一个或多个形状相关联，其表示单元设计的共同特征，导致多个连接形状。 从第一基本布局​​或第二基本布局开始，改变每个链接形状的顶点的位置，以产生单元格设计的变体布局。

    Differential FET structures for electrical monitoring of overlay
    4.
    发明授权
    Differential FET structures for electrical monitoring of overlay 失效
    用于覆盖层电气监控的差分FET结构

    公开(公告)号：US08409882B2

    公开(公告)日：2013-04-02

    申请号：US12617901

    申请日：2009-11-13

    申请人： Emrah Acar ,  Aditya Bansal ,  Amith Singhee

    发明人： Emrah Acar ,  Aditya Bansal ,  Amith Singhee

    IPC分类号： H01L21/66

    CPC分类号： G03F7/70633 ,  H01L22/34

    摘要： A method and apparatus for determining overlay includes an array of electronic devices having structures formed in a plurality of layers and such that a device on a first end of the array includes an offset from a position of a device on a second end of the array. A measurement device is configured to measure electrical characteristics of the devices in the array to determine a transition position between the electrical characteristics. A comparison device is configured to determine an overlay between the layers based on a device associated with the transition position.

    摘要翻译： 用于确定覆盖层的方法和装置包括具有形成在多个层中的结构的电子器件的阵列，并且使得阵列的第一端上的器件包括从阵列的第二端上的器件的位置的偏移。 测量装置被配置为测量阵列中的装置的电特性以确定电特性之间的转变位置。 比较设备被配置为基于与转换位置相关联的设备来确定层之间的覆盖。

    DIFFERENTIAL FET STRUCTURES FOR ELECTRICAL MONITORING OF OVERLAY
    5.
    发明申请
    DIFFERENTIAL FET STRUCTURES FOR ELECTRICAL MONITORING OF OVERLAY 失效
    用于覆盖电气监测的差分FET结构

    公开(公告)号：US20110115463A1

    公开(公告)日：2011-05-19

    申请号：US12617901

    申请日：2009-11-13

    申请人： Emrah Acar ,  Aditya Bansal ,  Amith Singhee

    发明人： Emrah Acar ,  Aditya Bansal ,  Amith Singhee

    IPC分类号： G01N27/00

    CPC分类号： G03F7/70633 ,  H01L22/34

    摘要： A method and apparatus for determining overlay includes an array of electronic devices having structures formed in a plurality of layers and such that a device on a first end of the array includes an offset from a position of a device on a second end of the array. A measurement device is configured to measure electrical characteristics of the devices in the array to determine a transition position between the electrical characteristics. A comparison device is configured to determine an overlay between the layers based on a device associated with the transition position.

    摘要翻译： 用于确定覆盖层的方法和装置包括具有形成在多个层中的结构的电子器件的阵列，并且使得阵列的第一端上的器件包括从阵列的第二端上的器件的位置的偏移。 测量装置被配置为测量阵列中的装置的电特性以确定电特性之间的转变位置。 比较设备被配置为基于与转换位置相关联的设备来确定层之间的覆盖。

    CIRCUIT-LEVEL VALIDATION OF COMPUTER EXECUTABLE DEVICE/CIRCUIT SIMULATORS
    6.
    发明申请
    CIRCUIT-LEVEL VALIDATION OF COMPUTER EXECUTABLE DEVICE/CIRCUIT SIMULATORS 失效
    计算机可执行装置/电路仿真器的电路电平验证

    公开(公告)号：US20110172979A1

    公开(公告)日：2011-07-14

    申请号：US12685108

    申请日：2010-01-11

    申请人： Aditya Bansal ,  Pamela Castalino ,  Dallas M. Lea ,  Amith Singhee

    发明人： Aditya Bansal ,  Pamela Castalino ,  Dallas M. Lea ,  Amith Singhee

    IPC分类号： G06G7/48

    CPC分类号： G06F17/5022 ,  G06F17/5036

    摘要： A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values.

    摘要翻译： 公开了一种用于评估模型的方法，其特征在于是计算机可执行装置和电路模拟器。 该方法包括接收设备的测量参数，哪些设备基本上与模拟电路实例相同或实际来自模拟电路实例。 该模型通过调整的输入参数执行，以生成电路实例属性的模拟值。 将这些模拟值与相同属性的测量值进行比较。 模型的好处是基于模拟值和测量值之间的直接或统计一致程度来确定的。

    Circuit-level validation of computer executable device/circuit simulators
    7.
    发明授权
    Circuit-level validation of computer executable device/circuit simulators 失效
    计算机可执行设备/电路模拟器的电路级验证

    公开(公告)号：US08606556B2

    公开(公告)日：2013-12-10

    申请号：US12685108

    申请日：2010-01-11

    申请人： Aditya Bansal ,  Pamela Castalino ,  Dallas M. Lea ,  Amith Singhee

    发明人： Aditya Bansal ,  Pamela Castalino ,  Dallas M. Lea ,  Amith Singhee

    IPC分类号： G06F17/50 ,  G06G7/62

    CPC分类号： G06F17/5022 ,  G06F17/5036

    摘要： A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values.

    摘要翻译： 公开了一种用于评估模型的方法，其特征在于是计算机可执行装置和电路模拟器。 该方法包括接收设备的测量参数，哪些设备基本上与模拟电路实例相同或实际来自模拟电路实例。 该模型通过调整的输入参数执行，以生成电路实例属性的模拟值。 将这些模拟值与相同属性的测量值进行比较。 模型的好处是基于模拟值和测量值之间的直接或统计一致程度来确定的。

    Power napping technique for accelerated negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) recovery
    8.
    发明授权
    Power napping technique for accelerated negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) recovery 有权
    用于加速负偏压温度不稳定性（NBTI）和/或正偏压温度不稳定性（PBTI）恢复的功率起搏技术

    公开(公告)号：US09086865B2

    公开(公告)日：2015-07-21

    申请号：US13544975

    申请日：2012-07-09

    申请人： Aditya Bansal ,  Jae-Joon Kim

    发明人： Aditya Bansal ,  Jae-Joon Kim

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26

    摘要： A logic circuit is operated in a normal mode, with a supply voltage coupled to a supply rail of the logic circuit, and with a ground rail of the logic circuit grounded; It is determined that at least a portion of the logic circuit has experienced degradation due to bias temperature instability. Responsive to the determining, the logic circuit is operated in a power napping mode, with the supply voltage coupled to the ground rail of the circuit, with the supply rail of the circuit grounded, and with primary inputs of the circuit toggled between logical zero and logical one at low frequency. A logic circuit and corresponding design structures are also provided.

    摘要翻译： 逻辑电路在正常模式下工作，其中电源电压耦合到逻辑电路的电源轨，并且逻辑电路的接地线接地; 确定逻辑电路的至少一部分由于偏置温度不稳定性而经历劣化。 响应于确定，逻辑电路以电源起跳模式操作，其中电源电压耦合到电路的接地轨，电路的电源轨接地，并且电路的主输入在逻辑0和 低频的逻辑电路。 还提供了逻辑电路和相应的设计结构。