公开(公告)号：US07212136B2

公开(公告)日：2007-05-01

申请号：US10555841

申请日：2004-05-05

Applicant: Engel Roza

Inventor： Engel Roza

IPC: H03M7/30

CPC classification number: H03M7/302 ,  H03M7/304

Abstract: A Recursive bit-stream converter (Rebic) having digital low pass filter and multi-bit quantizer means in a feedback arrangement and means to serialize digital words obtain a non-integer Rebic factor via at least two quantizers that are successively operative to serialize their digital words to the output of the converter.

Abstract translation: 具有反馈装置中的数字低通滤波器和多位量化器装置的递归位流转换器（Rebic）和串行化数字字的装置通过至少两个量化器获得非整数的再生因子，该量化器连续地可操作以串行数字化 字到转换器的输出。

公开(公告)号：US20060290540A1

公开(公告)日：2006-12-28

申请号：US10555841

申请日：2004-05-05

Applicant: Engel Roza

Inventor： Engel Roza

IPC: H03M7/34

CPC classification number: H03M7/302 ,  H03M7/304

Abstract: Recursive bit-stream converter (Rebic) for converting a multi-bit digital input signal to a single bit digital output signal comprising a digital low pass filter and multi-bit quantizer means in a feedback arrangement and means to serialize the digital words of the quantizer means. To obtain a non-integer Rebic factor the quantizer means comprise at least two quantizers that are successively operative to serialize their digital words to the output of the converter.

Abstract translation: 用于将多比特数字输入信号转换为单位数字输出信号的递归位流转换器（Rebic），该单位数字输出信号包括反馈装置中的数字低通滤波器和多位量化器装置，以及串行化量化器的数字字的装置 手段。 为了获得非整数的Rebic因子，量化器装置包括至少两个量化器，其连续地操作以将其数字字串行化为转换器的输出。

公开(公告)号：US07152086B2

公开(公告)日：2006-12-19

申请号：US10262387

申请日：2002-10-01

Applicant: Engel Roza

Inventor： Engel Roza

IPC: G06F17/17 ,  H03M7/00

CPC classification number: H03H17/045

Abstract: Method and arrangement for converting the sample rate of a higher sample rate discrete time signal to a lower sample rate discrete time signal or vice versa. A recursive signal processing algorithm with low pass filtering function is used, which entirely takes place at the lower sample rate. The impulse response of the low pass filtering function is a power series expansion

公开(公告)号：US4450564A

公开(公告)日：1984-05-22

申请号：US299436

申请日：1981-09-04

Applicant: Lambertus J. Meuleman ,  Abram van de Grijp ,  Engel Roza

Inventor： Lambertus J. Meuleman ,  Abram van de Grijp ,  Engel Roza

IPC: H04B10/00 ,  H01S5/042 ,  H01S5/0683 ,  H03C3/36 ,  H04B10/02 ,  H04B10/155 ,  H04B10/18 ,  H04B14/02 ,  H01S3/10

CPC classification number: H04B14/026 ,  H01S5/06835 ,  H03C3/36 ,  H04B10/504 ,  H04B10/564

Abstract: Apparatus for modulating the output signal of a converter for converting electric signals into other signals, for example optical signals. An analog signal is applied to a subtraction device (6) the output signal of which controls a limiter (7). The binary output signal thereof controls the semiconductor laser diode (1) which is coupled to a photo-sensitive detector (3) for producing a feedback signal. After being amplified in a broad-band amplifier (9) and integrated in an integrator (13), this feedback signal is applied to the subtraction device (6), so that the feedback signal is subtracted from the analog signal. Variations in the optical output signal due to a non-linear conversion characteristic of the laser diode (1) and due to an optical retroaction of the fibre (2) on the laser diode, as well as output noise and signal-dependent amplitude variations, are reduced by the negative feedback.

Abstract translation: 用于调制转换器的输出信号以将电信号转换为其它信号（例如光信号）的装置。 模拟信号被施加到其输出信号控制限幅器（7）的减法装置（6）。 其二进制输出信号控制耦合到光敏检测器（3）的半导体激光二极管（1）以产生反馈信号。 在宽带放大器（9）中放大并积分在积分器（13）中之后，该反馈信号被施加到减法器件（6），从而从模拟信号中减去反馈信号。 由于激光二极管（1）的非线性转换特性以及由于光纤（2）在激光二极管上的光学逆变而导致的光输出信号的变化以及输出噪声和信号相关幅度变化， 被负反馈减少。

公开(公告)号：US4816771A

公开(公告)日：1989-03-28

申请号：US46201

申请日：1987-05-04

Applicant: Engel Roza

Inventor： Engel Roza

IPC: H03F3/34 ,  H03G3/20 ,  H03L7/093 ,  H03F1/26

CPC classification number: H03G3/30 ,  H03L7/093

Abstract: An amplifier arrangement for reducing an unwanted d.c. offset of an amplitude-varying input signal, has a threshold circuit (A.sub.3, B.sub.3) and an amplifier stage (A.sub.1, B.sub.1) coupled thereto, which threshold circuit (A.sub.3, B.sub.3) is provided with a bistable trigger circuit (A.sub.4, B.sub.4). This bistable trigger circuit (A.sub.4, B.sub.4) reduces the d.c. level of the input signal or output signal of the amplifier stage (A.sub.1, B.sub.1) in a steplike manner when this d.c. level increases. The bistable trigger circuit (A.sub.4, B.sub.4) has a hysteresis which is larger than the maximum amplitude variation of the input signal as a result of the desired signal component, so that a linear amplification of this desired signal component is possible and, in the case of a non-varying d.c. level, variations of the input signal due to the desired signal component cannot give rise to a d.c. reduction. This amplifier arrangement may be used in a phase-locked loop of a directly mixing synchronous AM receiver, which phase-locked loop is used for generating a synchronous local carrier in order to increase the input dynamic range of the receiver.

公开(公告)号：US4815102A

公开(公告)日：1989-03-21

申请号：US107624

申请日：1987-10-09

Applicant: Engel Roza

Inventor： Engel Roza

IPC: H04L7/027 ,  H04L25/60

CPC classification number: H04L7/027

Abstract: A clock generator for a pulse repeater of a receiver in a pulse transmission system comprises a forward filter (1) connected to its input (A), a difference former (2) whose positive input is connected to the output of the forward filter (1), a series arrangement connected between the output of the difference former (2) and the output (B) of the clock pulse generator and comprising a limiter (3), a time differentiator (4), a rectifier (5) and a narrow bandpass filter (10) in this order, and a feedback filter (6) connected between the output of the limiter (3) or the rectifier (5) and the negative input of the difference former (2). The limiter (3) is used to cancel intersymbol interference. The clock generator can be utilized in combination with a known pulse signal regenerator (1,7-9) of the decision feedback type to constitute a pulse repeater. Alternatively, a pulse repeater can be obtained by combining the clock generator with only a pulse regenerator (8, FIG. 2) whose clock input is connected to the output (B) of the clock generator, whose signal input is connected to the output of the rectifier (5) of the clock generator and whose output constitutes the output (c) of the pulse repeater.

公开(公告)号：US4210882A

公开(公告)日：1980-07-01

申请号：US859643

申请日：1977-12-12

Applicant: Engel Roza ,  Johannes O. Voorman

Inventor： Engel Roza ,  Johannes O. Voorman

IPC: H03H7/30 ,  H03H11/18 ,  H03H11/26 ,  H03H15/00 ,  H03H7/28 ,  H03H7/10 ,  H03H7/22

CPC classification number: H03H15/00 ,  H03H11/18 ,  H03H11/26

Abstract: A delay network, having a chain of all-pass sections, each comprising two separate branches, a resistive and a capacitive branch, which terminate in amplifiers with negligible signal consumption whose output signals are combined. This enables an analog delay network to be realized in integrated circuit technology.

Abstract translation: 具有全通部分链路的延迟网络，每个链路包括两个分离的分支，电阻和电容分支，其终止于输出信号被组合的具有可忽略的信号消耗的放大器。 这使得可以在集成电路技术中实现模拟延迟网络。

公开(公告)号：US4039967A

公开(公告)日：1977-08-02

申请号：US657558

申请日：1976-02-12

Applicant: Engel Roza

Inventor： Engel Roza

IPC: H04L25/40 ,  H03D13/00 ,  H03L7/06 ,  H03L7/085 ,  H04B3/36 ,  H03B3/04

CPC classification number: H03D13/009 ,  H03L7/085 ,  H04B3/36

Abstract: A phase-locked loop circuit in which the phase offset error arising from imperfections in the balance of the phase comparator is reduced to a minimum by a special construction of the phase comparator. The quasi-static phase error of the loop is then reduced to very low values so that the loop is particularly suited for recovering the clock frequency from synchronous pulse signals having clock frequencies of several hundred MHz.

公开(公告)号：US3962635A

公开(公告)日：1976-06-08

申请号：US541727

申请日：1975-01-17

Applicant: Engel Roza

Inventor： Engel Roza

IPC: H04L25/52 ,  H04L7/027 ,  H04L7/033 ,  H04B7/14

CPC classification number: H04L7/027

Abstract: A transmission system for pulse signals of fixed clock frequency with regenerative repeaters located in the transmission path, each being provided with a pulse regenerator and a clock extraction circuit recovering the clock frequency for the control of the pulse regenerator from the received pulse signals with the aid of a frequency selective circuit. The use of a special type of frequency selective circuit results, especially in transmission systems having a large number of regenerative repeaters, in a considerable reduction of the phase jitter of the recovered clock signal in the receiver without detrimentally influencing the acquisition of the clock frequency in the individual regenerative repeaters.

Abstract translation: 一种传输系统，用于固定时钟频率的脉冲信号，具有位于传输路径中的再生中继器，每个传输路径均设置有脉冲再生器和时钟提取电路，从辅助的接收到的脉冲信号中恢复脉冲再生器的控制时钟频率 的频率选择电路。 特别是在具有大量再生中继器的传输系统中使用特殊类型的频率选择电路的结果显着地降低了接收机中恢复的时钟信号的相位抖动，而不会不利地影响时钟频率的获取 各个再生中继器。

公开(公告)号：US06215434B1

公开(公告)日：2001-04-10

申请号：US09129808

申请日：1998-08-06

Applicant: Engel Roza

Inventor： Engel Roza

IPC: H03M160

CPC classification number: H03M1/504

Abstract: A method and arrangement for converting an analog input signal into a digital output signal. The analog input signal is converted into a duty cycle modulated square wave. For reducing the communication rate of the digital output signal a time frame of subsampling periods is created and, within each subsampling period, the position of samples, which approximately coincide with the transients of the square wave, is determined. The invention further provides an image sensor comprising a plurality of such arrangements.

Abstract translation: 一种用于将模拟输入信号转换为数字输出信号的方法和装置。 模拟输入信号被转换成占空比调制方波。 为了降低数字输出信号的通信速率，产生子采样周期的时间帧，并且在每个子采样周期内确定与方波的瞬变近似一致的样本的位置。 本发明还提供一种包括多个这样的布置的图像传感器。