公开(公告)号：US20060179239A1

公开(公告)日：2006-08-10

申请号：US11054889

申请日：2005-02-10

申请人： Eric Fluhr ,  Bradly Frey ,  John Griswell ,  Hung Le ,  Cathy May ,  Francis O'Connell ,  Edward Silha ,  Albert Williams

发明人： Eric Fluhr ,  Bradly Frey ,  John Griswell ,  Hung Le ,  Cathy May ,  Francis O'Connell ,  Edward Silha ,  Albert Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US20080091922A1

公开(公告)日：2008-04-17

申请号：US11953637

申请日：2007-12-10

申请人： Eric Fluhr ,  Bradly Frey ,  John Griswell ,  Hung Le ,  Cathy May ,  Francis O'Connell ,  Edward Silha ,  Albert Williams

发明人： Eric Fluhr ,  Bradly Frey ,  John Griswell ,  Hung Le ,  Cathy May ,  Francis O'Connell ,  Edward Silha ,  Albert Williams

IPC分类号： G06F9/38

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

公开(公告)号：US20060179238A1

公开(公告)日：2006-08-10

申请号：US11054871

申请日：2005-02-10

申请人： John Griswell ,  Hung Le ,  Francis O'Connell ,  William Starke ,  Jeffrey Stuecheli ,  Albert Williams

发明人： John Griswell ,  Hung Le ,  Francis O'Connell ,  William Starke ,  Jeffrey Stuecheli ,  Albert Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0811

摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

摘要翻译： 在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。 预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。 预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。 预取引擎将预取队列中的条目与两个连续高速缓存块的窗口进行比较。 当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。 当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

公开(公告)号：US20070204108A1

公开(公告)日：2007-08-30

申请号：US11364620

申请日：2006-02-28

申请人： John Griswell ,  Francis O'Connell

发明人： John Griswell ,  Francis O'Connell

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0866 ,  G06F2212/6024

摘要： Computer implemented method, system and computer program product for prefetching data in a data processing system. A computer implemented method for prefetching data in a data processing system includes generating attribute information of prior data streams by associating attributes of each prior data stream with a storage access instruction which caused allocation of the data stream, and then recording the generated attribute information. The recorded attribute information is accessed, and a behavior of a new data stream is modified using the accessed recorded attribute information.

摘要翻译： 计算机实现方法，系统和计算机程序产品，用于在数据处理系统中预取数据。 一种用于在数据处理系统中预取数据的计算机实现方法包括通过将每个先前数据流的属性与导致数据流分配的存储访问指令相关联，然后记录所生成的属性信息来生成先前数据流的属性信息。 访问记录的属性信息，并且使用所访问的记录的属性信息来修改新的数据流的行为。

公开(公告)号：US20060161762A1

公开(公告)日：2006-07-20

申请号：US11039498

申请日：2005-01-20

申请人： Lee Eisen ,  David Levitan ,  Francis O'Connell ,  Wolfram Sauer

发明人： Lee Eisen ,  David Levitan ,  Francis O'Connell ,  Wolfram Sauer

IPC分类号： G06F9/44

CPC分类号： G06F9/5011 ,  G06F9/3844 ,  G06F9/3851 ,  G06F2209/507 ,  Y02D10/22

摘要： A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is low. The resource control applied may be the number of instruction fetches allocated to the thread or the number of execution time slices. Alternatively, or in combination, the size of a prefetch instruction storage allocated to the thread may be limited. The control condition may be comparison of the number of correct or incorrect speculations to a threshold, comparison of the number of correct to incorrect speculations, or a more complex evaluator such as the size of a ratio of incorrect to total speculations.

摘要翻译： 用于管理用于推测性执行的处理系统资源使用的方法和逻辑装置降低与程序指令的无效推测执行相关联的功率和性能负担。 投机执行效率的度量用于减少分配给线程的资源，同时投机效率低。 应用的资源控制可以是分配给线程的指令获取的数量或执行时间片的数量。 或者或组合地，分配给线程的预取指令存储器的大小可能受到限制。 控制条件可以是正确的或不正确的猜测的数量与阈值的比较，正确到不正确的猜测的数量的比较，或比较复杂的评估者，比如不正确比例与总猜测的比例。

公开(公告)号：US20050138613A1

公开(公告)日：2005-06-23

申请号：US10855729

申请日：2004-05-27

申请人： Roch Archambault ,  Robert Blainey ,  Yaoqing Gao ,  John McCalpin ,  Francis O'Connell ,  Pascal Vezolle ,  Steven White

发明人： Roch Archambault ,  Robert Blainey ,  Yaoqing Gao ,  John McCalpin ,  Francis O'Connell ,  Pascal Vezolle ,  Steven White

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F12/02

CPC分类号： G06F8/4442

摘要： A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a modification factor for the instructions based on a number of separate equivalent sections forming a cache in a processor which is processing the instructions; and modifying the instructions to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.

摘要翻译： 提供了修改形成循环的指令的方法和系统。 修改形成循环的指令的方法包括修改形成循环的指令，包括：确定指令的静态和动态特性; 基于在正在处理所述指令的处理器中形成高速缓存的单独的等效部分的数量来选择所述指令的修改因子; 以及当指令满足基于静态和动态特性的修改标准时，修改指令以根据修改因子和静态和动态特性来交织循环中的指令。

公开(公告)号：US20060048120A1

公开(公告)日：2006-03-02

申请号：US10926595

申请日：2004-08-26

申请人： Rock Archambault ,  Robert Blainey ,  Yaoqing Gao ,  Allan Martin ,  James McInnes ,  Francis O'Connell

发明人： Rock Archambault ,  Robert Blainey ,  Yaoqing Gao ,  Allan Martin ,  James McInnes ,  Francis O'Connell

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.

公开(公告)号：US20060149944A1

公开(公告)日：2006-07-06

申请号：US11002522

申请日：2004-12-02

申请人： Lee Eisen ,  Francis O'Connell

发明人： Lee Eisen ,  Francis O'Connell

IPC分类号： G06F9/44

CPC分类号： G06F9/3842 ,  G06F9/30058 ,  G06F9/30181 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3867

摘要： A method, apparatus, and computer program product are disclosed for selectively prohibiting speculative conditional branch execution. A particular type of conditional branch instruction is selected. An indication is stored within each instruction that is the particular type of conditional branch instruction. A processor then fetches a first instruction from code that is to be executed. A determination is made regarding whether the first instruction includes the indication. In response to determining that the instruction includes the indication: speculative execution of the first instruction is prohibited, an actual location to which the first instruction will branch is resolved, and execution of the code is branched to the actual location. In response to determining that the instruction does not include the indication, the first instruction is speculatively executed.

摘要翻译： 公开了用于选择性地禁止推测性条件分支执行的方法，装置和计算机程序产品。 选择特定类型的条件分支指令。 指示存储在作为条件分支指令的特定类型的每个指令内。 然后处理器从要执行的代码中获取第一条指令。 确定第一指令是否包括指示。 响应于确定指令包括指示：禁止第一指令的推测执行，第一指令将分支的实际位置被解析，并且代码的执行被分支到实际位置。 响应于确定指令不包括指示，推测性地执行第一指令。