Compressed instruction format for use in a VLIW processor and processor
for processing such instructions
    10.
    发明授权
    Compressed instruction format for use in a VLIW processor and processor for processing such instructions 失效
    用于VLIW处理器和处理器的压缩指令格式用于处理此类指令

    公开(公告)号:US5878267A

    公开(公告)日:1999-03-02

    申请号:US86696

    申请日:1998-05-29

    摘要: Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

    摘要翻译: 软件为VLIW处理器创建一个压缩指令格式,可以提高高速缓存和内存的使用效率。 指令是字节对齐和可变长度。 分支目标未压缩。 格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。 个别操作根据特征进行压缩,例如是否无结果,守卫,简短,零,一元或二进制。 指令以压缩形式存储在内存和缓存中。 从高速缓存中读出指令后即可解除指令。