-
1.发明授权Computer graphics system utilizing parallel processing for enhanced performance 失效使用并行处理的计算机图形系统提高性能
公开(公告)号：US5821950A
公开(公告)日：1998-10-13
申请号：US634458
申请日：1996-04-18
CPC分类号： G06T15/005 , G06T1/20
摘要： A computer graphics system includes a plurality of geometry accelerators for processing vertex data representative of graphics primitives and providing rendering data. The system includes a distributor responsive to a stream of vertex data for distributing to the geometry accelerators chunks of the vertex data for processing by the geometry accelerators to provide chunks of rendering data. The distributor generates an end of chunk bit indicative of the end of each of the chunks of vertex data. The system further includes a concentrator for receiving the chunks of rendering data from each of the geometry accelerators and for combining the chunks of rendering data into a stream of rendering data in response to end of chunk bits. The stream of rendering data and the stream of vertex data represent sequences of graphics primitives having the same order. A rasterizer generates pixel data representative of a graphics display in response to the stream of rendering data.
摘要翻译： 计算机图形系统包括多个几何加速器，用于处理表示图形原语的顶点数据并提供呈现数据。 该系统包括响应于顶点数据流的分布器，用于分布到几何加速器顶点数据的块中，用于由几何加速器处理以提供重绘数据块。 分配器生成指示每个顶点数据块的结束的块位的结尾。 该系统还包括一个收集器，用于从每个几何加速器接收渲染数据的块，并且响应于块位的结尾将渲染数据的块组合成渲染数据流。 渲染数据流和顶点数据流表示具有相同顺序的图形基元的序列。 光栅化器响应于渲染数据流生成表示图形显示的像素数据。
-
2.发明授权Caching and coherency control of multiple geometry accelerators in a computer graphics system 失效计算机图形系统中多个几何加速器的缓存和一致性控制
公开(公告)号：US5969726A
公开(公告)日：1999-10-19
申请号：US866909
申请日：1997-05-30
CPC分类号： G06T15/005
摘要： A computer graphics system for rendering graphics primitives based upon primitive data received from a host computer through a graphics interface includes a plurality of geometry accelerators. A distributor divides the primitive data into chunks of primitive data and distributes the chunks to a current geometry accelerator recipient. A state controller is configured to store and resend selected primitive data to the geometry accelerators based upon whether one or more vertices of a graphics primitive are contained in more than one of the chunks of primitive data. Advantageously, this enables the computer graphics system to efficiently process primitive data while avoiding providing the geometry accelerators with an excessive amount of data than necessary for them to render the primitives. Specifically, the state controller includes in the selected primitive data vertex states which were sent to a previous current geometry accelerator recipient and which are required by the current geometry accelerator recipient to assemble at least a portion of the graphics primitive. In addition, the state controller resends the property states to the current geometry accelerator recipient when the currently-stored local state in the current geometry accelerator recipient is not the same as a currently-effective local state. Furthermore, when the resent vertex states include a first and second resent vertex state, the selected primitive data includes property states which changed from when the first vertex state was sent to the previous current geometry accelerator and the second vertex state was sent to the previous current geometry accelerator.
摘要翻译： 用于基于通过图形接口从主计算机接收的原始数据来渲染图形基元的计算机图形系统包括多个几何加速器。 分销商将原始数据划分成原始数据块，并将块分配给当前的几何加速器收件人。 状态控制器被配置为基于图形基元的一个或多个顶点是否包含在原始数据块中的多于一个的块中，将所选择的原始数据存储并重新发送到几何加速器。 有利地，这使得计算机图形系统能够有效地处理原始数据，同时避免向几何加速器提供比它们渲染图元所需的数据量过大的数据。 具体地说，状态控制器包括被选择的原始数据顶点状态，这些顶点状态被发送到先前的当前几何加速器接收者，并且当前的几何加速器接收者需要它来组装图形原语的至少一部分。 此外，当当前几何加速器收件人当前存储的本地状态与当前有效的本地状态不同时，状态控制器会将属性状态重新发送到当前几何加速器接收方。 此外，当重新发送的顶点状态包括第一和第二重新顶点状态时，所选择的原始数据包括从第一顶点状态被发送到先前的当前几何加速器而改变并且第二顶点状态被发送到先前电流的属性状态 几何加速器
-
公开(公告)号：US08959398B2
公开(公告)日：2015-02-17
申请号：US13587631
申请日：2012-08-16
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.
摘要翻译： 具有调试功能的集成电路包括：第一封隔器和同步器，用于组合从第一电路接收的第一触发信号的多个值，以形成第一打包触发信号，并响应触发器输出同步的第一打包触发信号 时钟信号，第一触发信号与第一源时钟信号同步;第一逻辑门，用于提供第一输出触发信号，指示第一同步打包触发信号中第一触发信号的第一多个数值是否为第一触发信号 处于第一状态，并且调试状态机响应于第一输出触发信号选择性地提供第一动作信号。
-
4.发明授权Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad 失效存储器控制器具有能够交替地产生一个或多个数据流的接收机电路，作为在数据焊盘处接收数据，响应于在选通焊盘处接收到的选通沿的计数公开(公告)号：US07103793B2
公开(公告)日：2006-09-05
申请号：US10685940
申请日：2003-10-14
CPC分类号： G06F13/1689
摘要： A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).
摘要翻译： 双数据速率存储器控制器设置有多个数据和选通焊盘，用于经由所述焊盘以1x双倍数据速率存储器速度接收数据和选通信号的装置，以及用于经由所述焊盘以Mx双倍数据接收数据和选通信号的装置 速率记忆速度（M2）。
-
公开(公告)号：US06633965B2
公开(公告)日：2003-10-14
申请号：US09828604
申请日：2001-04-07
IPC分类号： G06F1200
CPC分类号： G06F13/1689
摘要： Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.
摘要翻译： 本文公开了从存储器接收数据的方法和装置，与选通相关联的数据。 通常，所述方法和装置为存储器控制器提供了以不同速率接收数据的装置。 数据可以由存储器控制器以不同的速率接收，因为例如，存储器控制器用于其直接连接到多个存储器模块的环境中，和/或在其经由多个存储器模块附接到多个存储器模块的环境中使用 中介芯片 中间芯片可以例如包括从两个或多个存储器模块组接收数据的多路复用器，然后将数据复用到一个或多个数据流中，然后将数据流以两倍于存储器模块的速率传输到存储器控制器 银行可以将数据发送到内存控制器。
-
公开(公告)号：US5671373A
公开(公告)日：1997-09-23
申请号：US480607
申请日：1995-06-08
摘要： An apparatus and method for transferring data between first and second circuit blocks of a computer graphics system are provided. The first and second circuit blocks are interconnected by a data bus having n bits. The apparatus includes a circuit in the first circuit block for sequentially transmitting data words from the first circuit block to a second circuit block on the data bus. The data words include one or more long data words having more than n bits. The apparatus further includes a register in the first circuit block for storing bits of the long data words in excess of n bits, and a controller in the first circuit block for loading the bits of the long data words in excess of n bits into the register and for combining the bits of the long data words stored in the register into a composite data word for transmission to the second circuit block. The composite data word may include a short data word having less than n bits. In a preferred embodiment, Z coordinate data words having 40 bits are transmitted with an 8 bit command word over a 32 bit data bus without extra bus cycles.
摘要翻译： 提供了一种用于在计算机图形系统的第一和第二电路块之间传送数据的装置和方法。 第一和第二电路块通过具有n位的数据总线相互连接。 该装置包括在第一电路块中用于将数据字从第一电路块顺序发送到数据总线上的第二电路块的电路。 数据字包括具有多于n位的一个或多个长数据字。 该装置还包括：第一电路块中用于存储超过n位的长数据字的位的寄存器;以及第一电路块中的控制器，用于将超过n位的长数据字的位加载到寄存器 并且将存储在寄存器中的长数据字的位组合成用于传输到第二电路块的复合数据字。 复合数据字可以包括具有小于n位的短数据字。 在优选实施例中，具有40位的Z坐标数据字通过32位数据总线以8位命令字发送，而不需要额外的总线周期。
-
公开(公告)号：US20140053027A1
公开(公告)日：2014-02-20
申请号：US13587631
申请日：2012-08-16
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/34
CPC分类号： G06F11/3656
摘要： An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.
摘要翻译： 具有调试功能的集成电路包括：第一封隔器和同步器，用于组合从第一电路接收的第一触发信号的多个值以形成第一打包触发信号，并响应触发器输出同步的第一打包触发信号 时钟信号，第一触发信号与第一源时钟信号同步;第一逻辑门，用于提供第一输出触发信号，指示第一同步打包触发信号中第一触发信号的第一多个数值是否为第一触发信号 处于第一状态，并且调试状态机响应于第一输出触发信号选择性地提供第一动作信号。
-
公开(公告)号：US20140032801A1
公开(公告)日：2014-01-30
申请号：US13557756
申请日：2012-07-25
申请人： Scott P. Nixon , Tiger Lu Lu , Eric M. Rentschler
发明人： Scott P. Nixon , Tiger Lu Lu , Eric M. Rentschler
IPC分类号： G06F13/00
CPC分类号： G06F11/364 , G06F11/3648
摘要： The present invention provides a method and apparatus for dynamically configuring debug triggering patterns. One example embodiment of the method includes comparing values of bits received on a first subset of a plurality of lines of a bus with a first pattern of bits and capturing values of bits received on a second subset of the plurality of lines of the bus in response to the comparison indicating that the values of the bits received on the first subset of the lines match the first pattern of bits. The exemplary embodiment of the method also includes defining a second pattern for triggering a debug action using the captured values.
摘要翻译： 本发明提供一种用于动态配置调试触发模式的方法和装置。 该方法的一个示例性实施例包括比较在总线的多条线路的第一子集上接收的比特值与第一比特模式，并响应于在总线的多条线路的第二子集上接收的比特值 比较指示在第一子集上接收的比特的值与第一种比特模式相匹配。 该方法的示例性实施例还包括使用捕获的值定义用于触发调试动作的第二模式。
-
公开(公告)号：US20130159780A1
公开(公告)日：2013-06-20
申请号：US13328512
申请日：2011-12-16
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/3419 , G06F11/348 , G06F2201/835 , G06F2201/88
摘要： An apparatus, processor, and method for synchronizing trace data. A processor includes multiple cores, and each core operates at a different local clock frequency. A global clock is distributed to each core, and a timestamp is generated using the global clock and the local clock. The timestamp and a local clock saturation value are included in each trace entry, and the local clock saturation value is equal to the ratio between the local clock and the global clock. The trace entries from separate cores are time-correlated in a post-processing phase based on the timestamp and local clock saturation values.
摘要翻译： 用于同步跟踪数据的装置，处理器和方法。 处理器包括多个核心，并且每个核心以不同的本地时钟频率运行。 全局时钟分配给每个核心，并使用全局时钟和本地时钟生成时间戳。 时间戳和本地时钟饱和值包含在每个跟踪条目中，本地时钟饱和值等于本地时钟与全局时钟之间的比率。 基于时间戳和本地时钟饱和度值，来自独立核心的跟踪条目在后处理阶段是时间相关的。
-
10.发明授权公开(公告)号：US06625702B2
公开(公告)日：2003-09-23
申请号：US09827766
申请日：2001-04-07
IPC分类号： G06F1200
CPC分类号： G06F13/1678 , G06F12/04
摘要： A memory controller that reads and writes memory modules populated with non-homogeneous data width RAM devices, wherein the RAM devices are of a type which send and receive data with a source synchronous strobe. The memory controller maintains a memory map and stores therein indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The indications of data/strobe ratios are addressed during read and write cycles of the memory controller. Addressed indications are used during write cycles to ensure that strobes are generated at a correct number of strobe pads. Addressed indications are used during read cycles to ensure that received data signals are associated with their correct and corresponding strobe signals.
-
-
-
-
-
-
-
-
-
搜索结果
30 条记录 (耗时 0.031 秒)
