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    Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices
    1.
    发明授权
    Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices 有权

    公开(公告)号：US06625702B2

    公开(公告)日：2003-09-23

    申请号：US09827766

    申请日：2001-04-07

    Applicant: Eric M. Rentschler ,  Jeffrey G. Hargis ,  George T Letey

    Inventor： Eric M. Rentschler ,  Jeffrey G. Hargis ,  George T Letey

    IPC: G06F1200

    CPC classification number: G06F13/1678 ,  G06F12/04

    Abstract: A memory controller that reads and writes memory modules populated with non-homogeneous data width RAM devices, wherein the RAM devices are of a type which send and receive data with a source synchronous strobe. The memory controller maintains a memory map and stores therein indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The indications of data/strobe ratios are addressed during read and write cycles of the memory controller. Addressed indications are used during write cycles to ensure that strobes are generated at a correct number of strobe pads. Addressed indications are used during read cycles to ensure that received data signals are associated with their correct and corresponding strobe signals.

    Memory controller to communicate with memory devices that are associated with differing data/strobe ratios
    2.
    发明授权
    Memory controller to communicate with memory devices that are associated with differing data/strobe ratios 失效
    存储器控制器与与不同数据/选通比率相关联的存储器件通信

    公开(公告)号：US06990562B2

    公开(公告)日：2006-01-24

    申请号：US10685929

    申请日：2003-10-14

    Applicant: Eric M. Rentschler ,  Jeffrey G. Hargis ,  George T. Letey

    Inventor： Eric M. Rentschler ,  Jeffrey G. Hargis ,  George T. Letey

    IPC: G06F12/00

    CPC classification number: G06F13/1689

    Abstract: A memory controller is provided with a memory to store indications of data/strobe ratios that are required to access memory devices that are coupled to the memory controller. The memory controller is also provided with a memory interface through which the memory controller initiates data transmissions with the memory devices. For a data transmission initiated with a particular one of the memory devices, the ratio of data signals to strobe signals sent/received through the interface is dynamically determined in response to a corresponding indication of a data/strobe ratio stored in the memory.

    Abstract translation: 存储器控制器设置有存储器，用于存储访问耦合到存储器控制器的存储器件所需的数据/选通比率的指示。 存储器控制器还具有存储器接口，存储器控制器通过存储器接口与存储器件发起数据传输。 对于利用特定存储器件发起的数据传输，响应于存储在存储器中的数据/选通比率的对应指示来动态地确定数据信号与通过接口发送/接收的选通信号的比率。

    Memory controller receiver circuitry with tri-state noise immunity
    5.
    发明授权
    Memory controller receiver circuitry with tri-state noise immunity 有权
    具有三态噪声抗扰度的存储器控​​制器接收器电路

    公开(公告)号：US06889335B2

    公开(公告)日：2005-05-03

    申请号：US09828041

    申请日：2001-04-07

    Applicant: Jeffrey G. Hargis ,  Eric M. Rentschler ,  Leith L. Johnson

    Inventor： Jeffrey G. Hargis ,  Eric M. Rentschler ,  Leith L. Johnson

    IPC: G06F13/16 ,  G06F13/40 ,  G06F1/04

    CPC classification number: G06F13/1684 ,  G06F13/4086

    Abstract: Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.

    Abstract translation: 本文公开了用于为诸如DDR存储器系统的存储器系统提供三态噪声抗扰性的方法和装置，其中1）读取数据环路延迟有很大变化，以及2）选通总线具有类似的终止和阈值电压。 在一个实施例中，选通接收机电路包括计数器和计数器控制逻辑。 该计数器响应于所接收的选通信号的选通沿来更新计数。 通过相对于所接收的选通信号异步地产生控制信号，计数器控制逻辑使得在接收每个选通信号之前的计数器。 计数器控制逻辑还通过从计数器接收反馈而接收到每个选通信号之后复位计数器，并且响应于该反馈，相对于所接收的选通信号来异步地重置计数器。 选通接收器电路可以形成DDR存储器控制器的一部分。

    Memory controller with 1X/MX write capability
    6.
    发明授权
    Memory controller with 1X/MX write capability 有权
    具有1X / MX写入能力的内存控制器

    公开(公告)号：US06678811B2

    公开(公告)日：2004-01-13

    申请号：US09827768

    申请日：2001-04-07

    Applicant: Eric M. Rentschler ,  Jeffrey G. Hargis ,  Leith L. Johnson

    Inventor： Eric M. Rentschler ,  Jeffrey G. Hargis ,  Leith L. Johnson

    IPC: G06F1300

    CPC classification number: G06F13/1689

    Abstract: Methods and apparatus for writing data to memory are disclosed herein. In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may need to be written to memory at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise demultiplexers which receive data from the memory controller at twice the rate which data could be written directly to a memory module. The intermediary chip may then simultaneously transmit the demultiplexed write data to memory modules in two or more banks of memory modules.

    Abstract translation: 本文公开了将数据写入存储器的方法和装置。 通常，方法和装置为存储器控制器提供以不同速率写入数据的装置。 数据可能需要以不同的速率写入存储器，因为例如，存储器控制器在其直接连接到多个存储器模块的环境中使用，和/或在其经由多个存储器模块附接到多个存储器模块的环境中使用 中介芯片 中间芯片可以例如包括解复用器，其以从该数据可以直接写入存储器模块的速率的两倍来从存储器控制器接收数据。 中间芯片然后可以同时将解复用的写入数据发送到两个或更多个存储器模块组中的存储器模块。

    Memory controller with 1×/M× read capability
    8.
    发明授权
    Memory controller with 1×/M× read capability 失效
    具有1x / Mx读取功能的内存控制器

    公开(公告)号：US06633965B2

    公开(公告)日：2003-10-14

    申请号：US09828604

    申请日：2001-04-07

    Applicant: Eric M. Rentschler ,  Jeffrey G. Hargis ,  Leith L. Johnson

    Inventor： Eric M. Rentschler ,  Jeffrey G. Hargis ,  Leith L. Johnson

    IPC: G06F1200

    CPC classification number: G06F13/1689

    Abstract: Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.

    Abstract translation: 本文公开了从存储器接收数据的方法和装置，与选通相关联的数据。 通常，所述方法和装置为存储器控制器提供了以不同速率接收数据的装置。 数据可以由存储器控制器以不同的速率接收，因为例如，存储器控制器用于其直接连接到多个存储器模块的环境中，和/或在其经由多个存储器模块附接到多个存储器模块的环境中使用 中介芯片 中间芯片可以例如包括从两个或多个存储器模块组接收数据的多路复用器，然后将数据复用到一个或多个数据流中，然后将数据流以两倍于存储器模块的速率传输到存储器控制器 银行可以将数据发送到内存控制器。

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