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1.发明授权Digital phase compensation methods and systems for a dual-channel analog-to-digital converter 有权用于双通道模数转换器的数字相位补偿方法和系统公开(公告)号：US06373415B1
公开(公告)日：2002-04-16
申请号：US09484480
申请日：2000-01-18
IPC分类号： H03M106
CPC分类号： G06J1/00
摘要： Phase compensation in a dual-channel analog-to-digital converter (ADC) is accomplished by holding conversion results in programmable length registers for controllable time periods. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing, is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay mechanism. A differential delay equal to &Dgr;I-&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADC's.
摘要翻译： 双通道模数转换器（ADC）中的相位补偿通过将可编程长度寄存器中的转换结果保持在可控时间段内来实现。 双通道ADC包括第一和第二Δ-Σ调制器和数字滤波器，受到多个采样率的优化，用于优化延迟的粗调和微调。 在采样数据域中执行能量计算，该采样数据域是使用在数字域中执行的延迟补偿方案中的数字乘法技术来实现的。 进行滤波处理的数字数据被延迟预定量。 双通道ADC具有可编程通道延迟机制。 校正和补偿等于DELTAI-DELTAV的差分延迟，受制于正确能量值的可接受时间延迟。 根据本发明的ADC进一步以接收到的ADC的输出速率的时钟速率对接收到的模拟信号进行过采样，并且在连接到ADC的下行滤波器中产生延迟。
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2.发明授权Delay correction system and method for a voltage channel in a sampled data measurement system 有权采样数据测量系统中电压通道的延迟校正系统和方法公开(公告)号：US06304202B1
公开(公告)日：2001-10-16
申请号：US09484866
申请日：2000-01-18
IPC分类号： H03M100
CPC分类号： G06J1/00
摘要： Delay correction in a dual-channel analog-to-digital converter (ADC) is accomplished by insertion of coarse and fine delay correction registers prior to and after a frequency reduction element in a voltage channel. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay adjustment in the voltage channel thereof. A delay differential equal to &Dgr;I−&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADCs.
摘要翻译： 在双通道模数转换器（ADC）中的延迟校正通过在电压通道中的频率降低元件之前和之后插入粗略和精细的延迟校正寄存器来实现。 双通道ADC包括第一和第二Δ-Σ调制器和数字滤波器，受到多个采样率的优化，用于优化延迟的粗调和微调。 在采样数据域中执行能量计算，该采样数据域是使用在数字域中执行的延迟补偿方案中的数字乘法技术来实现的。 进行滤波处理的数字数据被延迟预定量。 双通道ADC在其电压通道中提供可编程通道延迟调整。 等于DELTAI-DELTAV的延迟差分经过可靠的时间延迟进行校准和补偿，以产生正确的能量值。 根据本发明的ADC进一步以比ADC的输出速率高得多的时钟速率对接收到的模拟信号进行过采样，并且在连接到ADC的下游滤波器中产生延迟。
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3.发明授权Energy-to-pulse converter systems, devices, and methods wherein the output frequency is greater than the calculation frequency and having output phasing 有权能量到脉冲转换器系统，装置和方法，其中输出频率大于计算频率并具有输出相位公开(公告)号：US06522982B1
公开(公告)日：2003-02-18
申请号：US09405370
申请日：1999-09-24
IPC分类号： G01B1302
CPC分类号： G06J1/00
摘要： An energy-to-pulse (E2P) converter for converting analog voltage and current measurements into digital power consumption readout that has an improved output frequency range and can eliminate the potential information loss in a multiple-wires and multiple-phases power distribution system without added complex hardware. The E2P uses a threshold value T in determining the output pulse count which represents the energy/power consumption. The energy consumption E is updated every cycle of a first clock rate F1 during which a power P calculation is performed following a voltage V and a current I analog-to digital conversion. The updated energy consumption E is then divided by the threshold value T to determine the number of pulses that correspond to the power consumption. The number of pulses are output at a second clock rate F2. In so doing, more than one pulse can be generated for each P calculation thereby improving the output frequency range. To prevent complete signal overlaps that may lead to information loss in multiple-wires and multiple-phases power system, the pulse output for each wire can be programmed to have a different phase such that the pulses from the pulse outputs, which are all synchronous with each other, are non-overlapped.
摘要翻译： 一种用于将模拟电压和电流测量转换为数字功耗读数的能量脉冲（E2P）转换器，具有改进的输出频率范围，可以消除多线和多相配电系统中的潜在信息丢失，无需添加 复杂的硬件。 E2P在确定表示能量/功耗的输出脉冲计数时使用阈值T. 在第一时钟速率F1的每个周期更新能量消耗E，在第一时钟速率F1期间，在电压V和电流I模数转换之后执行功率P计算。 然后将更新的能量消耗E除以阈值T以确定与功耗相对应的脉冲数。 以第二时钟速率F2输出脉冲数。 这样做，可以为每个P计算产生多于一个脉冲，从而改善输出频率范围。 为了防止可能导致多线和多相电力系统中的信息丢失的完整的信号重叠，每条线路的脉冲输出可以被编程为具有不同的相位，使得来自脉冲输出的脉冲全部与 彼此不重叠。
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4.发明授权Single phase bi-directional electrical measurement systems and methods using ADCs 有权单相双向电气测量系统和使用ADC的方法公开(公告)号：US06417792B1
公开(公告)日：2002-07-09
申请号：US09484688
申请日：2000-01-18
申请人： Eric T. King , Douglas F. Pastorello , Bruce P. Del Signore , Victor Aguilar , Frank Den Breejen , William F. Gardei
发明人： Eric T. King , Douglas F. Pastorello , Bruce P. Del Signore , Victor Aguilar , Frank Den Breejen , William F. Gardei
IPC分类号： H03M300
CPC分类号： G01R21/133
摘要： An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase 2 or 3 wire power meters. Voltage and current are measured with a shunt or transformer, and a divider or transformer, respectively. The serial interface is bidirectional for communication with a microprocessor or controller, and provides a fixed width programmable frequency output proportional to energy. The digital converter system is user system calibratible.
摘要翻译： 模数转换器系统包括单个芯片上的第一和第二Δ-Σ转换器，计算引擎和串行接口。 计算引擎配置为计算单相2线或3线功率计的能量，功率，均方根电流和电压。 电压和电流分别用分流器或变压器以及分压器或变压器来测量。 串行接口是双向的，与微处理器或控制器通信，并提供与能量成比例的固定宽度的可编程频率输出。 数字转换器系统是用户系统校准的。
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公开(公告)号：US06657488B1
公开(公告)日：2003-12-02
申请号：US10036986
申请日：2001-12-31
IPC分类号： H03F102
CPC分类号： H03F3/087 , H03F3/45973 , H03F2200/331 , H03L7/06
摘要： A slice and offset circuit is provided that uses a digital integrator in the feedback loop of the offset cancellation circuitry. A slice circuit receives an indication of a desired slice voltage and supplies a signal to specify the slice level, which is combined with a sensed offset level of the amplifier. The feedback loop includes a low pass filter that receives the combined signal indicative of the offset and the slice level. The low pass filter includes the digital integrator circuit that includes an up/down counter that counts in a direction determined according to a digital signal having a ones-density indicative of a value of the combined signal with respect to a reference signal, thereby generating a feedback signal that cancels offset and adjusts for slice.
摘要翻译： 提供了在偏移消除电路的反馈回路中使用数字积分器的切片和偏移电路。 分片电路接收期望的片电压的指示，并提供信号以指定限幅电平，其与感测到的放大器的偏移电平组合。 反馈回路包括低通滤波器，其接收指示偏移和切片电平的组合信号。 低通滤波器包括数字积分器电路，其包括向上/向下计数器，该上/下计数器根据具有指示相对于参考信号的组合信号的值的1密度的数字信号确定的方向进行计数，从而生成 反馈信号取消偏移并调整切片。
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公开(公告)号：US06271778B1
公开(公告)日：2001-08-07
申请号：US09483826
申请日：2000-01-15
IPC分类号： H03M148
CPC分类号： H03H17/02
摘要： A system and method for selectively providing high pass filtering of two digital signals that are to be subsequently combined. Each of the first and second signals is passed through one of a high pass filter, an all-pass filter and a module that performs substantially no signal filtering, where the phase and magnitude for either high pass filter are substantially equal to the phase and magnitude for either all-pass filter. At the minimum, the system provides the following filtering combinations for the respective first signal and second signal: (no filter, no filter), (high pass, high pass), (high pass, all-pass) and (all-pass, high-pass). Suitable first order high pass and corresponding all-pass filters are determined.
摘要翻译： 一种用于选择性地提供将要被组合的两个数字信号的高通滤波的系统和方法。 第一和第二信号中的每一个通过高通滤波器，全通滤波器和基本上不执行信号滤波的模块之一，其中高通滤波器的相位和幅度基本上等于相位和幅度 用于全通滤波器。 至少，系统为相应的第一信号和第二信号提供以下滤波组合：（无滤波器，无滤波器），（高通，高通），（高通，全通）和（全通） 高通）。 确定合适的一阶高通和相应的全通滤波器。
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公开(公告)号：US07502434B2
公开(公告)日：2009-03-10
申请号：US10813243
申请日：2004-03-30
申请人： Eric T. King , Douglas Pastorello
发明人： Eric T. King , Douglas Pastorello
CPC分类号： H04L7/0337 , H03L7/113
摘要： A frequency detector and frequency-locked loop suitable for use in a clock recovery circuit are disclosed. The detector is linear, and can be used in implementing a loss of lock indicator. Variable delay filtering permits the frequency detector to be less sensitive to data fluctuations, and random or pseudo random addition of jitter helps address low gain in the data stream. A VCO controller cycles through a number of control states and provides varying levels of gain, dither and delay during each of the control states.
摘要翻译： 公开了一种适用于时钟恢复电路的频率检测器和频率锁相环。 检测器是线性的，可用于实现锁定指示器的丢失。 可变延迟滤波允许频率检测器对数据波动较不敏感，并且抖动的随机或伪随机添加有助于解决数据流中的低增益。 VCO控制器循环多个控制状态，并在每个控制状态期间提供不同程度的增益，抖动和延迟。
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公开(公告)号：US06232821B1
公开(公告)日：2001-05-15
申请号：US09483801
申请日：2000-01-15
申请人： Eric T. King , Bruce P. Del Signore
发明人： Eric T. King , Bruce P. Del Signore
IPC分类号： H03K1716
CPC分类号： H03K19/01735 , H02M3/07 , H02M2001/009 , H02M2003/071 , H03K19/01714
摘要： A capacitively isolated input system that permits sensing of an input voltage with a below-ground value or a below-substrate voltage value. Multiple input signals are received, and each input signal is connected to cross-connected switching components. Switched output signals are capacitively connected to additional switching components and to a sensing amplifier. This system allows the sensing amplifier to receive capacitively isolated input signals and to provide corresponding output signals at voltages no lower than ground voltage.
摘要翻译： 一种电容隔离的输入系统，其允许以低于地面值或低于基板电压值的输入电压进行感测。 接收多个输入信号，每个输入信号连接到交叉连接的开关组件。 开关输出信号电容连接到附加的开关部件和感测放大器。 该系统允许感测放大器接收电容隔离的输入信号，并在不低于接地电压的电压下提供相应的输出信号。
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公开(公告)号：US08207788B2
公开(公告)日：2012-06-26
申请号：US12082081
申请日：2008-04-07
申请人： Wai L. Lee , Patrick A. Quinn , Garry N. Link , Adam C. Broun , Eric T. King
发明人： Wai L. Lee , Patrick A. Quinn , Garry N. Link , Adam C. Broun , Eric T. King
IPC分类号： H03F3/217
CPC分类号： H03F1/301 , H03F1/342 , H03F3/2173
摘要： A differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the PSRR of the amplifier. In another aspect of the present invention, a differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the CMRR of the amplifier. In a further aspect of the present invention, a Class D amplifier is provided with a passive differential feedback, summing with an input current at a differential virtual ground produced by an amplifier which is a sub-section of the Class D amplifier.
摘要翻译： 差分反馈放大器设置有反馈网络，其中反馈网络是可调节的，以便改善放大器的PSRR。 在本发明的另一方面，差分反馈放大器设置有反馈网络，其中反馈网络是可调节的，以便改善放大器的CMRR。 在本发明的另一方面，D类放大器被提供有无源差分反馈，与由作为D类放大器的子部分的放大器产生的差分虚拟接地处的输入电流相加。
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公开(公告)号：US20080272842A1
公开(公告)日：2008-11-06
申请号：US12082081
申请日：2008-04-07
申请人： Wai L. Lee , Patrick A. Quinn , Garry N. Link , Adam C. Broun , Eric T. King
发明人： Wai L. Lee , Patrick A. Quinn , Garry N. Link , Adam C. Broun , Eric T. King
CPC分类号： H03F1/301 , H03F1/342 , H03F3/2173
摘要： A differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the PSRR of the amplifier. In another aspect of the present invention, a differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the CMRR of the amplifier. In a further aspect of the present invention, a Class D amplifier is provided with a passive differential feedback, summing with an input current at a differential virtual ground produced by an amplifier which is a sub-section of the Class D amplifier.
摘要翻译： 差分反馈放大器设置有反馈网络，其中反馈网络是可调节的，以便改善放大器的PSRR。 在本发明的另一方面，差分反馈放大器设置有反馈网络，其中反馈网络是可调节的，以便改善放大器的CMRR。 在本发明的另一方面，D类放大器被提供有无源差分反馈，与由作为D类放大器的子部分的放大器产生的差分虚拟接地处的输入电流相加。
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