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公开(公告)号：US09785434B2
公开(公告)日：2017-10-10
申请号：US13241673
申请日：2011-09-23
CPC分类号： G06F9/30021 , G06F7/544 , G06F9/30036 , G06F17/18
摘要： An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.
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公开(公告)号：US20130080490A1
公开(公告)日：2013-03-28
申请号：US13241673
申请日：2011-09-23
IPC分类号： G06F7/02
CPC分类号： G06F9/30021 , G06F7/544 , G06F9/30036 , G06F17/18
摘要： An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.
摘要翻译： 公开了一种确定极值的装置，系统和方法。 参考位置标识符和参考极值被耦合。 确定输入数据集的输入极值，并确定输入极值的相应位置标识符。 基于比较，将输入极值与参考极值进行比较，以确定输出极值和输出位置标识符。
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3.发明授权Executing instruction packet with multiple instructions with same destination by performing logical operation on results of instructions and storing the result to the destination 有权通过对指令结果执行逻辑运算并将结果存储到目的地，执行具有相同目的地的多个指令的指令包公开(公告)号：US08843730B2
公开(公告)日：2014-09-23
申请号：US13228601
申请日：2011-09-09
CPC分类号： G06F9/38 , G06F9/30072 , G06F9/30094 , G06F9/3853
摘要： An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.
摘要翻译： 一种装置包括处理器和耦合到处理器的存储器。 存储器存储包括第一谓词独立指令和第二谓词独立指令的指令分组（例如，VLIW指令分组）。 每个谓词独立指令具有相同的目的地。
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4.发明申请INSTRUCTION PACKET INCLUDING MULTIPLE INSTRUCTIONS HAVING A COMMON DESTINATION 有权指令包，其中包括具有公共目的地的多种指令公开(公告)号：US20130067205A1
公开(公告)日：2013-03-14
申请号：US13228601
申请日：2011-09-09
CPC分类号： G06F9/38 , G06F9/30072 , G06F9/30094 , G06F9/3853
摘要： An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.
摘要翻译： 一种装置包括处理器和耦合到处理器的存储器。 存储器存储包括第一谓词独立指令和第二谓词独立指令的指令分组（例如，VLIW指令分组）。 每个谓词独立指令具有相同的目的地。
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公开(公告)号：US08756601B2
公开(公告)日：2014-06-17
申请号：US13241407
申请日：2011-09-23
申请人： Erich J. Plondke , Lucian Codrescu
发明人： Erich J. Plondke , Lucian Codrescu
IPC分类号： G06F9/455 , G06F9/46 , G06F15/173
CPC分类号： G06F9/4856
摘要： A system and method for memory coherency acceleration via virtual machine migration comprises a plurality of processors. A first processor of the plurality of processors is configured to implement at least one virtual machine. A monitor is configured to monitor a number of memory requests between the first processor and at least a second processor of the plurality of processors. A virtual machine manager is configured to migrate at least a portion of the virtual machine from the first processor to the second processor based on the number of memory requests exceeding a threshold.
摘要翻译： 通过虚拟机迁移的用于存储器一致性加速的系统和方法包括多个处理器。 多个处理器中的第一处理器被配置为实现至少一个虚拟机。 监视器被配置为监视第一处理器与多个处理器中的至少第二处理器之间的多个存储器请求。 虚拟机管理器被配置为基于超过阈值的存储器请求的数量将虚拟机的至少一部分从第一处理器迁移到第二处理器。
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公开(公告)号：US20130080738A1
公开(公告)日：2013-03-28
申请号：US13241775
申请日：2011-09-23
申请人： Erich J. Plondke , Ajay A. Ingle , Lucian Codrescu
发明人： Erich J. Plondke , Ajay A. Ingle , Lucian Codrescu
CPC分类号： G06F9/3834 , G06F9/3851 , G06F9/3853
摘要： In a particular embodiment, a very long instruction word (VLIW) processor is operable to execute VLIW instructions. At least one of the VLIW instructions includes a first load or store instruction and a second load or store instruction. The first instruction and the second instruction are executed as a single atomic unit. At least one of the first and second instructions is a store-conditional instruction.
摘要翻译： 在特定实施例中，非常长的指令字（VLIW）处理器可操作以执行VLIW指令。 至少一个VLIW指令包括第一加载或存储指令以及第二加载或存储指令。 第一条指令和第二条指令作为一个原子单位执行。 第一和第二指令中的至少一个是存储条件指令。
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7.发明申请公开(公告)号：US20100118852A1
公开(公告)日：2010-05-13
申请号：US12690213
申请日：2010-01-20
CPC分类号： G06F9/30101 , G06F9/30021 , G06F9/30094 , G06F9/3885
摘要： A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.
摘要翻译： 公开了一种处理数据的方法，包括执行从存储器单元获取多个指令。 该方法还包括将多个指令分组为不同类型的指令包，以由多个指令执行单元并行执行。 指令包包括第一指令和第二指令。 该方法包括使用组合标量和向量条件码寄存器来执行用于比较操作的第一指令和使用组合标量和向量条件码寄存器的条件操作的第二指令。 该方法还包括当比较操作是标量比较操作时，在指令执行单元处接收用于标量比较操作的标量比较指令，并存储组合标量和向量条件代码寄存器中的标量比较操作的结果。
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公开(公告)号：US20130081013A1
公开(公告)日：2013-03-28
申请号：US13241407
申请日：2011-09-23
申请人： Erich J. Plondke , Lucian Codrescu
发明人： Erich J. Plondke , Lucian Codrescu
IPC分类号： G06F9/455
CPC分类号： G06F9/4856
摘要： A system and method for memory coherency acceleration via virtual machine migration comprises a plurality of processors. A first processor of the plurality of processors is configured to implement at least one virtual machine. A monitor is configured to monitor a number of memory requests between the first processor and at least a second processor of the plurality of processors. A virtual machine manager is configured to migrate at least a portion of the virtual machine from the first processor to the second processor based on the number of memory requests exceeding a threshold.
摘要翻译： 通过虚拟机迁移的用于存储器一致性加速的系统和方法包括多个处理器。 多个处理器中的第一处理器被配置为实现至少一个虚拟机。 监视器被配置为监视第一处理器与多个处理器中的至少第二处理器之间的多个存储器请求。 虚拟机管理器被配置为基于超过阈值的存储器请求的数量将虚拟机的至少一部分从第一处理器迁移到第二处理器。
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9.发明授权公开(公告)号：US08190854B2
公开(公告)日：2012-05-29
申请号：US12690213
申请日：2010-01-20
CPC分类号： G06F9/30101 , G06F9/30021 , G06F9/30094 , G06F9/3885
摘要： A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.
摘要翻译： 公开了一种处理数据的方法，包括执行从存储器单元获取多个指令。 该方法还包括将多个指令分组为不同类型的指令包，以由多个指令执行单元并行执行。 指令包包括第一指令和第二指令。 该方法包括使用组合标量和向量条件码寄存器来执行用于比较操作的第一指令和使用组合标量和向量条件码寄存器的条件操作的第二指令。 该方法还包括当比较操作是标量比较操作时，在指令执行单元处接收用于标量比较操作的标量比较指令，并存储组合标量和向量条件代码寄存器中的标量比较操作的结果。
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公开(公告)号：US10289412B2
公开(公告)日：2019-05-14
申请号：US13369693
申请日：2012-02-09
IPC分类号： G06F9/30
摘要： Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.
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