公开(公告)号：US20100318742A1

公开(公告)日：2010-12-16

申请号：US12482529

申请日：2009-06-11

申请人： Erich James Plondke ,  Lucian Codrescu ,  Ajay Ingle

发明人： Erich James Plondke ,  Lucian Codrescu ,  Ajay Ingle

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F12/121 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/127

摘要： In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.

摘要翻译： 在特定实施例中，电路设备包括被配置为接收虚拟地址并将虚拟地址转换为具有至少两个分区的高速缓存的物理地址的翻译后备缓冲器（TLB）。 电路装置还包括控制逻辑电路，其适于基于分区指示符来识别与所识别的至少两个分区中的一个分区相关联的分区替换策略。 控制逻辑电路响应于高速缓存未命中事件，根据所识别的分区替换策略来控制高速缓存内的数据的替换。

公开(公告)号：US08250332B2

公开(公告)日：2012-08-21

申请号：US12482529

申请日：2009-06-11

申请人： Erich James Plondke ,  Lucian Codrescu ,  Ajay Ingle

发明人： Erich James Plondke ,  Lucian Codrescu ,  Ajay Ingle

IPC分类号： G06F12/00

CPC分类号： G06F12/121 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/127

摘要： In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.

摘要翻译： 在特定实施例中，电路设备包括被配置为接收虚拟地址并将虚拟地址转换为具有至少两个分区的高速缓存的物理地址的翻译后备缓冲器（TLB）。 电路装置还包括控制逻辑电路，其适于基于分区指示符来识别与所识别的至少两个分区中的一个分区相关联的分区替换策略。 控制逻辑电路响应于高速缓存未命中事件，根据所识别的分区替换策略来控制高速缓存内的数据的替换。

公开(公告)号：US20070100923A1

公开(公告)日：2007-05-03

申请号：US11266076

申请日：2005-11-02

申请人： Muhammad Ahmed ,  Ajay Ingle ,  Sujat Jamil

发明人： Muhammad Ahmed ,  Ajay Ingle ,  Sujat Jamil

IPC分类号： G06F7/42

CPC分类号： G06F9/30181 ,  G06F9/30032 ,  G06F9/3012 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3885

摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.

摘要翻译： 公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供 以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。 此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及 移位输出以提供移位数据。

公开(公告)号：US20060268592A1

公开(公告)日：2006-11-30

申请号：US11137183

申请日：2005-05-25

申请人： Baker Mohammad ,  Muhammad Ahmed ,  Paul Bassett ,  Sujat Jamil ,  Ajay Ingle

发明人： Baker Mohammad ,  Muhammad Ahmed ,  Paul Bassett ,  Sujat Jamil ,  Ajay Ingle

IPC分类号： G11C15/00

CPC分类号： G06F12/0895 ,  G06F12/0864 ,  G06F12/0893

摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.