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    Register file system and method for pipelined processing
    1.
    发明授权
    Register file system and method for pipelined processing 有权
    注册文件系统和流水线处理方法

    公开(公告)号：US08725991B2

    公开(公告)日：2014-05-13

    申请号：US11853866

    申请日：2007-09-12

    申请人： Lin Wang ,  Masud Kamal ,  Paul Bassett ,  Suresh Venkumahanti ,  Jian Shen

    发明人： Lin Wang ,  Masud Kamal ,  Paul Bassett ,  Suresh Venkumahanti ,  Jian Shen

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/30141 ,  G06F13/4252 ,  Y02D10/14 ,  Y02D10/151

    摘要： The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a pipeline access position that is non-sequential to the second thread. A method of accessing a plurality of register files is also disclosed. The method includes reading data from a first register file while concurrently reading data from a second register file. The first register file is associated with a first instruction stream and the second register file is associated with a second instruction stream. The first instruction stream is sequential to the second instruction stream in an execution pipeline of a processor, and the first register file is in a non-adjacent location with respect to the second register file.

    摘要翻译： 本公开包括多线程处理器，其包括与第一线程相关联的第一寄存器文件和与第二线程相关联的第二寄存器文件。 至少一个硬件资源由第一和第二寄存器文件共享。 此外，第一线程可以具有与第二线程不连续的管线访问位置。 还公开了一种访问多个寄存器文件的方法。 该方法包括从第一寄存器文件读取数据，同时从第二寄存器堆读取数据。 第一寄存器文件与第一指令流相关联，并且第二寄存器文件与第二指令流相关联。 第一指令流在处理器的执行流水线中与第二指令流相顺序，并且第一寄存器文件相对于第二寄存器文件位于非相邻位置。

    Logic device and method supporting scan test
    2.
    发明授权
    Logic device and method supporting scan test 有权
    支持扫描测试的逻辑设备和方法

    公开(公告)号：US07992062B2

    公开(公告)日：2011-08-02

    申请号：US11473219

    申请日：2006-06-22

    申请人： Martin Saint-Laurent ,  Paul Bassett ,  Prayag Patel

    发明人： Martin Saint-Laurent ,  Paul Bassett ,  Prayag Patel

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318552 ,  G01R31/3025 ,  G01R31/318575

    摘要： A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.

    摘要翻译： 逻辑器件包括数据输入，扫描测试输入，时钟解复用器和主锁存器。 时钟解复用器响应于时钟输入以选择性地提供第一时钟输出和第二时钟输出。 主锁存器耦合到数据输入和扫描测试输入，并包括输出。 主锁存器响应于时钟解复用器的第一时钟输出和时钟解复用器的第二时钟输出，以选择性地将数据输入或扫描测试输入耦合到输出。

    Clock gating system and method
    3.
    发明授权
    Clock gating system and method 有权
    时钟门控系统和方法

    公开(公告)号：US07902878B2

    公开(公告)日：2011-03-08

    申请号：US12431992

    申请日：2009-04-29

    申请人： Martin Saint-Laurent ,  Bassam Jamil Mohd ,  Paul Bassett

    发明人： Martin Saint-Laurent ,  Bassam Jamil Mohd ,  Paul Bassett

    IPC分类号： H03K19/096

    CPC分类号： H03K19/0016 ,  G06F1/04

    摘要： A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

    摘要翻译： 公开了时钟选通系统和方法。 在特定实施例中，系统包括输入逻辑电路，该输入逻辑电路具有至少一个输入端以接收至少一个输入信号并在内部使能节点具有输出。 保持器电路包括响应于门控时钟信号的至少一个开关元件，并且耦合到内部使能节点以选择性地保持内部使能节点处的逻辑电压电平。 该系统还包括响应于输入时钟信号和内部使能节点处的逻辑电压电平的选通元件，以产生门控时钟信号。

    Low power microprocessor cache memory and method of operation
    5.
    发明授权
    Low power microprocessor cache memory and method of operation 有权
    低功耗微处理器缓存存储器和操作方法

    公开(公告)号：US07620778B2

    公开(公告)日：2009-11-17

    申请号：US11137183

    申请日：2005-05-25

    申请人： Baker Mohammad ,  Muhammad Ahmed ,  Paul Bassett ,  Sujat Jamil ,  Ajay Anant Ingle

    发明人： Baker Mohammad ,  Muhammad Ahmed ,  Paul Bassett ,  Sujat Jamil ,  Ajay Anant Ingle

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0895 ,  G06F12/0864 ,  G06F12/0893

    摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.

    摘要翻译： 用于处理包括使用数字信号处理器的通信（例如，CDMA）系统中的传输的技术。 数字信号处理器包括高速缓冲存储器系统，并将多个高速缓冲存储器匹配线与可寻址存储器的可寻址存储器线相关联。 每个高速缓存存储器匹配行与高速缓冲存储器的相应组中的一个相关联。 该方法和系统将每个缓存存储器匹配线保持在低电压。 一旦数字信号处理器启动对高速缓冲存储器的搜索，以从相应的高速缓冲存储器组中的选定的一个中选出一个数据，则匹配线驱动电路将高速缓冲存储器匹配线之一从低电压驱动到高电压。 高速缓存存储器匹配行中所选择的一个对应于高速缓冲存储器的所选择的相应组中的一个。 数字信号处理器将所选择的一个高速缓冲存储器匹配线与可寻址存储器线中的相关联的一个进行比较。 在比较步骤之后，该过程将高速缓存存储器匹配行之一返回到低电压。

    FISHING LINE CONTROL SYSTEM
    7.
    发明公开
    FISHING LINE CONTROL SYSTEM 审中-公开

    公开(公告)号：US20240065241A1

    公开(公告)日：2024-02-29

    申请号：US18387224

    申请日：2023-11-06

    申请人： Jeffrey Paul Bassett

    发明人： Jeffrey Paul Bassett

    IPC分类号： A01K87/04

    CPC分类号： A01K87/04

    摘要： A fishing device is disclosed including a fishing rod and a line guide connected to the fishing rod. A moveable or pivoting lever may be disposed adjacent to the line guide. A fishing line braking surface may disposed adjacent to the lever. The lever may be used to press the fishing line against the braking surface to slow or stop it from passing through the line guide. A finger control at the rod handle may be used to move the lever into a braking position.

    Register File System and Method for Pipelined Processing
    8.
    发明申请
    Register File System and Method for Pipelined Processing 有权
    注册文件系统和流水线处理方法

    公开(公告)号：US20090070554A1

    公开(公告)日：2009-03-12

    申请号：US11853866

    申请日：2007-09-12

    申请人： Lin Wang ,  Masud Kamal ,  Paul Bassett ,  Suresh Venkumahanti ,  Jian Shen

    发明人： Lin Wang ,  Masud Kamal ,  Paul Bassett ,  Suresh Venkumahanti ,  Jian Shen

    IPC分类号： G06F9/40

    CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/30141 ,  G06F13/4252 ,  Y02D10/14 ,  Y02D10/151

    摘要： The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a pipeline access position that is non-sequential to the second thread. A method of accessing a plurality of register files is also disclosed. The method includes reading data from a first register file while concurrently reading data from a second register file. The first register file is associated with a first instruction stream and the second register file is associated with a second instruction stream. The first instruction stream is sequential to the second instruction stream in an execution pipeline of a processor, and the first register file is in a non-adjacent location with respect to the second register file.

    摘要翻译： 本公开包括多线程处理器，其包括与第一线程相关联的第一寄存器文件和与第二线程相关联的第二寄存器文件。 至少一个硬件资源由第一和第二寄存器文件共享。 此外，第一线程可以具有与第二线程不连续的管线访问位置。 还公开了一种访问多个寄存器文件的方法。 该方法包括从第一寄存器文件读取数据，同时从第二寄存器堆读取数据。 第一寄存器文件与第一指令流相关联，并且第二寄存器文件与第二指令流相关联。 第一指令流在处理器的执行流水线中与第二指令流相顺序，并且第一寄存器文件相对于第二寄存器文件位于非相邻位置。

    Sequential Circuit Element Including A Single Clocked Transistor
    9.
    发明申请
    Sequential Circuit Element Including A Single Clocked Transistor 有权
    包括单时钟晶体管的顺序电路元件

    公开(公告)号：US20090058463A1

    公开(公告)日：2009-03-05

    申请号：US11845950

    申请日：2007-08-28

    申请人： Martin Saint-Laurent ,  Baker Mohammad ,  Paul Bassett

    发明人： Martin Saint-Laurent ,  Baker Mohammad ,  Paul Bassett

    IPC分类号： H03K3/02

    CPC分类号： H03K3/356121 ,  G06F9/3869

    摘要： A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path.

    摘要翻译： 公开了一种方法，其包括响应于在顺序电路元件的单个时钟晶体管处接收的时钟信号，经由时序电路元件的第一数据路径传播数据。 该方法还包括保持与在第二数据路径的保持电路元件处经由第一路径传播的数据有关的信息，其中第一数据路径包括响应于单个时钟晶体管的输出的第一晶体管。 第一晶体管具有比与第二数据路径相关联的第二晶体管更高的电流流动能力。