公开(公告)号：US20070266288A1

公开(公告)日：2007-11-15

申请号：US11435064

申请日：2006-05-15

申请人： Erik Volkerink ,  Hugh Wallace ,  Klaus-Dieter Hilliges ,  Ajay Khoche ,  Jochen Rivoir

发明人： Erik Volkerink ,  Hugh Wallace ,  Klaus-Dieter Hilliges ,  Ajay Khoche ,  Jochen Rivoir

IPC分类号： G01R31/28

CPC分类号： G01R31/31907

摘要： An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associated with each re-configurable test processor. The communications include configuration information, control information, communication protocols, stimulus data, and responses. Configuration information and stimulus data can also be read from a memory. Configuration information is used to configure one or more re-configurable test processors. Once configured, the re-configurable test processor or processors process the data in order to generate one or more test signals. The one or more test signals are then used to test a DUT.

摘要翻译： 自适应测试系统包括一个或多个可重新配置的测试板，每个测试板包括至少一个可重新配置的测试处理器。 可重新配置的测试处理器可以使用与每个可重新配置的测试处理器相关联的处理器间通信控制器彼此进行通信。 通信包括配置信息，控制信息，通信协议，刺激数据和响应。 还可以从存储器读取配置信息和激励数据。 配置信息用于配置一个或多个可重新配置的测试处理器。 一旦配置，可重新配置的测试处理器或处理器处理数据，以产生一个或多个测试信号。 然后使用一个或多个测试信号来测试DUT。

公开(公告)号：US07590903B2

公开(公告)日：2009-09-15

申请号：US11435064

申请日：2006-05-15

申请人： Erik Volkerink ,  Hugh S. C. Wallace ,  Klaus-Dieter Hilliges ,  Ajay Khoche ,  Jochen Rivoir

发明人： Erik Volkerink ,  Hugh S. C. Wallace ,  Klaus-Dieter Hilliges ,  Ajay Khoche ,  Jochen Rivoir

IPC分类号： G01R31/28 ,  G11C29/00 ,  G06F11/00

CPC分类号： G01R31/31907

摘要： An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associated with each re-configurable test processor. The communications include configuration information, control information, communication protocols, stimulus data, and responses. Configuration information and stimulus data can also be read from a memory. Configuration information is used to configure one or more re-configurable test processors. Once configured, the re-configurable test processor or processors process the data in order to generate one or more test signals. The one or more test signals are then used to test a DUT.

摘要翻译： 自适应测试系统包括一个或多个可重新配置的测试板，每个测试板包括至少一个可重新配置的测试处理器。 可重新配置的测试处理器可以使用与每个可重新配置的测试处理器相关联的处理器间通信控制器彼此进行通信。 通信包括配置信息，控制信息，通信协议，刺激数据和响应。 还可以从存储器读取配置信息和激励数据。 配置信息用于配置一个或多个可重新配置的测试处理器。 一旦配置，可重新配置的测试处理器或处理器处理数据，以产生一个或多个测试信号。 然后使用一个或多个测试信号来测试DUT。

公开(公告)号：US07712000B2

公开(公告)日：2010-05-04

申请号：US11589465

申请日：2006-10-30

申请人： Ajay Khoche ,  Klaus-Dieter Hilliges

发明人： Ajay Khoche ,  Klaus-Dieter Hilliges

IPC分类号： G01R31/28

CPC分类号： G01R31/31704 ,  G01R31/319

摘要： An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK couples the hardware resources and software processes as needed for a first DFT testing block to be enabled for testing only when such resources and processes are available and locked for the first DFT testing block. The DPK is coupled to the first DFT testing blocks via data channels and control channels that are selected as needed for having the first DFT testing block enabled for testing. The channels are under the control of an DUTs-ATE interface which is directed by the DPK for connecting the first DFT testing block to the locked hardware resource and the locked software processes. Each set up process corresponding to any subsequent DFT testing block requesting any hardware resource and any software processes that are already locked for use is paused until such locked resource and locked software processes are unlocked and assigned for having that subsequent DFT testing block enabled for testing.

摘要翻译： 描述了一种ATE系统，用于在耦合到ATE系统时测试一个或多个DUT中包含的一个或多个DFT测试块。 ATE系统包括在DPK（分布式处理内核）控制下的硬件资源和软件过程。 DPK根据需要将硬件资源和软件过程与第一个DFT测试块相结合，仅在第一个DFT测试块可用并锁定此类资源和过程时进行测试。 DPK通过数据通道和控制通道耦合到第一个DFT测试块，根据需要选择第一个DFT测试块，以使第一个DFT测试块能够进行测试。 这些通道由DUT-ATE接口控制，由DPK引导，用于将第一个DFT测试块连接到锁定的硬件资源和锁定的软件进程。 与任何随后的DFT测试块对应的每个设置过程都将被暂停，直到锁定的资源和锁定的软件进程被解锁并被分配以使该后续的DFT测试块能够进行测试。

公开(公告)号：US20080104461A1

公开(公告)日：2008-05-01

申请号：US11589465

申请日：2006-10-30

申请人： Ajay Khoche ,  Klaus-Dieter Hilliges

发明人： Ajay Khoche ,  Klaus-Dieter Hilliges

IPC分类号： G01R31/28

CPC分类号： G01R31/31704 ,  G01R31/319

摘要： An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK couples the hardware resources and software processes as needed for a first DFT testing block to be enabled for testing only when such resources and processes are available and locked for the first DFT testing block. The DPK is coupled to the first DFT testing blocks via data channels and control channels that are selected as needed for having the first DFT testing block enabled for testing. The channels are under the control of an DUTs-ATE interface which is directed by the DPK for connecting the first DFT testing block to the locked hardware resource and the locked software processes. Each set up process corresponding to any subsequent DFT testing block requesting any hardware resource and any software processes that are already locked for use is paused until such locked resource and locked software processes are unlocked and assigned for having that subsequent DFT testing block enabled for testing.

摘要翻译： 描述了一种ATE系统，用于在耦合到ATE系统时测试一个或多个DUT中包含的一个或多个DFT测试块。 ATE系统包括在DPK（分布式处理内核）控制下的硬件资源和软件过程。 DPK根据需要将硬件资源和软件过程与第一个DFT测试块相结合，仅在第一个DFT测试块可用并锁定此类资源和过程时进行测试。 DPK通过数据通道和控制通道耦合到第一个DFT测试块，根据需要选择第一个DFT测试块，以使第一个DFT测试块能够进行测试。 这些通道由DUT-ATE接口控制，由DPK引导，用于将第一个DFT测试块连接到锁定的硬件资源和锁定的软件进程。 与任何随后的DFT测试块对应的每个设置过程都将被暂停，直到锁定的资源和锁定的软件进程被解锁并被分配以使该后续的DFT测试块能够进行测试。

公开(公告)号：US07797599B2

公开(公告)日：2010-09-14

申请号：US11535973

申请日：2006-09-27

申请人： Ajay Khoche ,  Klaus-Dieter Hilliges

发明人： Ajay Khoche ,  Klaus-Dieter Hilliges

IPC分类号： G01R31/28

CPC分类号： G01R31/318533

摘要： From a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, diagnostic information is obtained by using the scan chains to apply a stimulus vector to the logic circuits, to capture responses of the logic circuits to the stimulus vector and to shift the captured responses towards the outputs of the scan chains; generating a representative signature representing the responses output by the scan chains; concurrently storing the responses output by the scan chains temporarily such no more than a most-recently output subset of the responses is stored; determining whether the representative signature is a fault-indicating representative signature; and, when the representative signature is a fault-indicating representative signature, outputting at least some of the stored responses. The output responses are usable as diagnostic information. The most-recently output subset of the responses is composed of fewer than all of the responses generated in response to the stimulus vector.

摘要翻译： 从包括逻辑电路和包含扫描链的内置自检系统（BIST））的逻辑设备，通过使用扫描链将训练矢量应用于逻辑电路获得诊断信息，以将逻辑电路的响应捕获到 刺激矢量并将捕获的响应移动到扫描链的输出; 生成表示由扫描链输出的响应的代表性签名; 同时存储由扫描链暂时输出的响应，不再存储响应的最近的输出子集; 确定代表性签名是否是故障指示代表签名; 并且当所述代表性签名是故障指示代表签名时，输出所存储的响应中的至少一些。 输出响应可用作诊断信息。 响应的最近的输出子集由少于响应于刺激矢量而产生的全部响应组成。

公开(公告)号：US20080092003A1

公开(公告)日：2008-04-17

申请号：US11535973

申请日：2006-09-27

申请人： Ajay Khoche ,  Klaus-Dieter Hilliges

发明人： Ajay Khoche ,  Klaus-Dieter Hilliges

IPC分类号： G01R31/28

CPC分类号： G01R31/318533

摘要： From a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, diagnostic information is obtained by using the scan chains to apply a stimulus vector to the logic circuits, to capture responses of the logic circuits to the stimulus vector and to shift the captured responses towards the outputs of the scan chains; generating a representative signature representing the responses output by the scan chains; concurrently storing the responses output by the scan chains temporarily such no more than a most-recently output subset of the responses is stored; determining whether the representative signature is a fault-indicating representative signature; and, when the representative signature is a fault-indicating representative signature, outputting at least some of the stored responses. The output responses are usable as diagnostic information. The most-recently output subset of the responses is composed of fewer than all of the responses generated in response to the stimulus vector.

摘要翻译： 从包括逻辑电路和包含扫描链的内置自检系统（BIST））的逻辑设备，通过使用扫描链将训练矢量应用于逻辑电路获得诊断信息，以将逻辑电路的响应捕获到 刺激矢量并将捕获的响应移动到扫描链的输出; 生成表示由扫描链输出的响应的代表性签名; 同时存储由扫描链暂时输出的响应，不再存储响应的最近的输出子集; 确定代表性签名是否是故障指示代表签名; 并且当所述代表性签名是故障指示代表签名时，输出所存储的响应中的至少一些。 输出响应可用作诊断信息。 响应的最近的输出子集由少于响应于刺激矢量而产生的全部响应组成。

公开(公告)号：US20080077834A1

公开(公告)日：2008-03-27

申请号：US11535979

申请日：2006-09-27

申请人： Ajay Khoche ,  Klaus-Dieter Hilliges

发明人： Ajay Khoche ,  Klaus-Dieter Hilliges

IPC分类号： G01R31/28

CPC分类号： G11C29/40 ,  G11C2029/0405

摘要： From a memory device comprising a memory circuit and a built-in self-test system (BIST), diagnostic information is deterministically obtained by using the BIST to perform a test sequence that tests the memory circuit. The test sequence comprises writing one or more test patterns at memory locations in the memory circuit and reading respective output patterns from the memory locations. Diagnostic patterns corresponding to the output patterns are losslessly compressed to generate compressed diagnostic information. The compressed diagnostic information is temporarily stored and, at one or more predetermined points in the test sequence, the compressed diagnostic information is output from the memory device under test. Losslessly compressing the diagnostic patterns and outputting the resulting compressed diagnostic information at predetermined points in the test sequence provides the diagnostic information deterministically, which allows the diagnostic information to be received by conventional, deterministically-operating ATE.

摘要翻译： 从包括存储器电路和内置自检系统（BIST）的存储器件中，通过使用BIST来确定性地获得诊断信息，以执行测试存储器电路的测试序列。 测试序列包括在存储器电路中的存储器位置处写入一个或多个测试图案，并从存储器位置读取相应的输出图案。 对应于输出模式的诊断模式被无损压缩以产生压缩的诊断信息。 压缩的诊断信息被临时存储，并且在测试序列中的一个或多个预定点处，从被测试的存储器件输出压缩的诊断信息。 在测试序列中的预定点无损压缩诊断模式并输出所得到的压缩诊断信息，确定性地提供诊断信息，这允许通过传统的确定性操作的ATE来接收诊断信息。

公开(公告)号：US07137053B2

公开(公告)日：2006-11-14

申请号：US09946857

申请日：2001-09-04

申请人： Ajay Khoche ,  Jochen Rivoir ,  David H. Armstrong

发明人： Ajay Khoche ,  Jochen Rivoir ,  David H. Armstrong

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318555

摘要： An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.

公开(公告)号：US20210012626A1

公开(公告)日：2021-01-14

申请号：US16923060

申请日：2020-07-07

申请人： Erik Volkerink ,  Ajay Khoche

发明人： Erik Volkerink ,  Ajay Khoche

IPC分类号： G08B5/36

摘要： Embodiments disclosed herein generally relate to line-powered wireless communications systems, and more specifically to methods and apparatus for providing persistent and ubiquitous wireless communications and sensor networks in physical premises to enable a wide variety of different applications and use cases.

公开(公告)号：US20140002121A1

公开(公告)日：2014-01-02

申请号：US14003414

申请日：2011-03-22

申请人： Ajay Khoche ,  Erik Volkerink

发明人： Ajay Khoche ,  Erik Volkerink

IPC分类号： G01R31/28

CPC分类号： G01R31/2851 ,  G01R31/318513 ,  H01L22/14 ,  H01L22/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00014

摘要： Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

摘要翻译： 提供系统和方法用于测试部分完成的三维IC。 示例性方法可以包括一个或多个以下特征：用于测试的设计（DFT）; 部分晶圆测试设计; 部分探测设计; 部分IC问题; 部分IC测试设备; 部分IC质量测定; 部分IC测试优化; 和部分测试优化。 还可以包括其他方面。 结合这些特征来测试部分完成的三维IC的系统和方法可以节省时间和精力，并且减少刮擦材料，因为当检测到不良部分装置时，部分装置不再进一步构建。 这导致较低的成本和更高的产量。