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    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods
    1.
    发明申请
    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods 审中-公开
    用于制造具有降低的对闩锁敏感性的半导体器件结构和通过该方法形成的半导体器件结构的方法

    公开(公告)号：US20070194403A1

    公开(公告)日：2007-08-23

    申请号：US11360345

    申请日：2006-02-23

    申请人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    发明人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L21/76

    CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

    摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体方法和器件结构。 该方法包括在衬底的半导体材料中形成沟槽，其第一侧壁设置在也在衬底的半导体材料中定义的一对掺杂阱之间。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩蔽沟槽的基底，随后去除暴露在部分屏蔽的基底上的衬底的半导体材料，以限定加深沟槽的变窄的第二侧壁。 加深的沟槽填充有介电材料以限定用于内置于掺杂阱中的器件的沟槽隔离区域。 填充沟槽加深的介质材料增强了闩锁抑制。

    WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES
    2.
    发明申请
    WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES 失效
    用于CMOS器件的绝缘隔离（WIT）

    公开(公告)号：US20070241408A1

    公开(公告)日：2007-10-18

    申请号：US11759981

    申请日：2007-06-08

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

    摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

    摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

    Methods and semiconductor structures for latch-up suppression using a conductive region
    6.
    发明申请
    Methods and semiconductor structures for latch-up suppression using a conductive region 失效
    使用导电区域进行闩锁抑制的方法和半导体结构

    公开(公告)号：US20070170543A1

    公开(公告)日：2007-07-26

    申请号：US11340752

    申请日：2006-01-26

    申请人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0921 ,  H01L21/823878 ,  H01L29/78

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 半导体结构包括形成在衬底的半导体材料中的第一和第二相邻的掺杂阱。 在第一和第二掺杂阱之间的衬底中限定了包括基底和基底与顶表面之间的第一侧壁的沟槽。 沟槽部分地填充有与第一和第二掺杂阱电耦合的导体材料。 可以在与沟槽中的导电材料相邻的位置处与沟槽邻接的半导体材料中提供高度掺杂的导电区域。

    Methods and semiconductor structures for latch-up suppression using a buried conductive region
    8.
    发明申请
    Methods and semiconductor structures for latch-up suppression using a buried conductive region 失效
    使用掩埋导电区域进行闩锁抑制的方法和半导体结构

    公开(公告)号：US20070158755A1

    公开(公告)日：2007-07-12

    申请号：US11330689

    申请日：2006-01-12

    申请人： Shunhua Chang ,  Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Shunhua Chang ,  Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0921 ,  H01L21/823878

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁接壤的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。

    SEMICONDUCTOR TRANSISTORS WITH CONTACT HOLES CLOSE TO GATES
    10.
    发明申请
    SEMICONDUCTOR TRANSISTORS WITH CONTACT HOLES CLOSE TO GATES 有权
    具有接触孔的半导体晶体管靠近门

    公开(公告)号：US20070102766A1

    公开(公告)日：2007-05-10

    申请号：US11163966

    申请日：2005-11-04

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  William Tonti

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  William Tonti

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114

    摘要： A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

    摘要翻译： 一种结构及其形成方法。 该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个 层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。