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    WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES
    3.
    发明申请
    WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES 失效
    用于CMOS器件的绝缘隔离（WIT）

    公开(公告)号：US20070241408A1

    公开(公告)日：2007-10-18

    申请号：US11759981

    申请日：2007-06-08

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

    摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

    摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods
    4.
    发明申请
    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods 审中-公开
    用于制造具有降低的对闩锁敏感性的半导体器件结构和通过该方法形成的半导体器件结构的方法

    公开(公告)号：US20070194403A1

    公开(公告)日：2007-08-23

    申请号：US11360345

    申请日：2006-02-23

    申请人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    发明人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L21/76

    CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

    摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体方法和器件结构。 该方法包括在衬底的半导体材料中形成沟槽，其第一侧壁设置在也在衬底的半导体材料中定义的一对掺杂阱之间。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩蔽沟槽的基底，随后去除暴露在部分屏蔽的基底上的衬底的半导体材料，以限定加深沟槽的变窄的第二侧壁。 加深的沟槽填充有介电材料以限定用于内置于掺杂阱中的器件的沟槽隔离区域。 填充沟槽加深的介质材料增强了闩锁抑制。

    Layout and process to contact sub-lithographic structures
    5.
    发明申请
    Layout and process to contact sub-lithographic structures 有权
    接触亚光刻结构的布局和工艺

    公开(公告)号：US20070215874A1

    公开(公告)日：2007-09-20

    申请号：US11378492

    申请日：2006-03-17

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

    IPC分类号： H01L23/58

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/528 ,  H01L2224/06 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

    摘要翻译： 一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。 第一和第二结构被嵌套，使得亚光刻线以平行方式设置在宽度内，并且第一结构的接触着陆段被设置在相对于子平版印刷线的相对侧的相对侧 第二结构的接触着陆段。 用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。

    REDUCED MASK COUNT GATE CONDUCTOR DEFINITION
    8.
    发明申请
    REDUCED MASK COUNT GATE CONDUCTOR DEFINITION 失效
    减少面罩计数门控导体定义

    公开(公告)号：US20060073394A1

    公开(公告)日：2006-04-06

    申请号：US10711758

    申请日：2004-10-04

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

    IPC分类号： G03C5/00 ,  G06F17/50 ,  G03F1/00

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

    摘要： A combined wide-image and loop-cutter pattern is provided for both cutting and forming a wide-image section to a hard mask on a substrate formed by sidewall imaging techniques in a reduced number of photolithographic steps. A single mask is formed which provides a wide mask section while additionally providing a mask to protect the critical edges of an underlying hard mask during hard mask etching. After the hard mask is cut into sections, the protective portions of the follow-on mask are removed to expose the critical edges of the underlying hard mask while maintaining shapes necessary for defining wide-image sections. Thus, the hard mask cutting, hard mask critical edge protecting, and large area mask may be formed in a reduced number of steps.

    摘要翻译： 提供了组合的宽图像和环形切割器图案，用于在通过减少数量的光刻步骤的侧壁成像技术形成的基板上切割和形成宽图像部分到硬掩模。 形成单个掩模，其提供宽掩模部分，同时另外提供掩模以在硬掩模蚀刻期间保护下面的硬掩模的临界边缘。 在将硬掩模切割成部分之后，除去后续掩模的保护部分以暴露下面的硬掩模的临界边缘，​​同时保持限定宽图像部分所需的形状。 因此，可以以减少的步数形成硬掩模切割，硬掩模临界边缘保护和大面积掩模。

    Methods for fabricating a metal-oxide-semiconductor device structure and metal-oxide-semiconductor device structures formed thereby
    10.
    发明申请
    Methods for fabricating a metal-oxide-semiconductor device structure and metal-oxide-semiconductor device structures formed thereby 有权
    制造金属氧化物半导体器件结构的方法和由此形成的金属氧化物半导体器件结构

    公开(公告)号：US20050242378A1

    公开(公告)日：2005-11-03

    申请号：US11175582

    申请日：2005-07-06

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/338 ,  H01L29/49 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

    CPC分类号： H01L29/66772 ,  H01L21/2807 ,  H01L29/4908

    摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

    摘要翻译： 一种制造金属氧化物半导体器件结构的方法。 该方法包括通过离子注入将掺杂剂物质同时引入覆盖在半导体有源层上的绝缘层和栅电极的半导体有源层中。 选择半导体有源层的厚度，栅电极的厚度和掺杂剂物质的动能，使得半导体有源层和绝缘层中的掺杂剂物质的投影范围位于绝缘层内，并且投影 栅电极中的掺杂物种类的范围位于栅电极内。 结果，半导体有源层和栅电极可以在单个离子注入期间同时掺杂，而不需要另外的注入掩模。