公开(公告)号：US07539920B2

公开(公告)日：2009-05-26

申请号：US11265451

申请日：2005-11-02

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

IPC分类号： H03M13/00

CPC分类号： H03M13/11

摘要： Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

摘要翻译： 提供了一种使用具有部分组的顺序解码算法的LDPC解码装置和方法，其能够将迭代解码的数量减少一半以上，而不降低性能并增加计算量。 LDPC解码方法包括以下步骤：基于与接收到的噪声相关的星座中的符号信号与LDPC编码数据之间的距离相关的信道值的信息，以及初始化比特节点，接收先验概率信息（信道值） 在根据先验概率信息更新校验节点信息之前，将校验节点划分为部分组，并通过应用顺序解码算法执行解码; 确定是否满足奇偶校验方程; 并输出在满足奇偶校验方程时获得的解码消息，或者通过终止算法终止迭代处理器。

公开(公告)号：US20060136799A1

公开(公告)日：2006-06-22

申请号：US11265451

申请日：2005-11-02

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

IPC分类号： H03M13/00

CPC分类号： H03M13/11

摘要： Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

公开(公告)号：US06732326B2

公开(公告)日：2004-05-04

申请号：US09846477

申请日：2001-04-30

申请人： Eun-A Choi ,  Jin-Ho Kim ,  Nae-Soo Kim ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Jin-Ho Kim ,  Nae-Soo Kim ,  Deock-Gil Oh

IPC分类号： H03M1341

CPC分类号： H03M13/6362 ,  H03M13/395 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107

摘要： A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams. This structure and this method can be applied to a depuncturing process for Radix-4 branch metric calculation of all punctured codes derived from ½ code.

摘要翻译： 在维特比解码器被设计成通过在设计维特比解码器的方法中设计的维特比解码器的结构和方法被输入到维特比解码器，该维特比解码器以高速解码穿孔码 ，被披露。 在高速维特比解码器中用于基数4分支度量计算的解穿孔结构包括四个FIFO，四个多路复用器和一个基数-4分支度量计算器。 I和Q的两个输入比特流连接到两个较高的FIFO和两个较低的FIFO。 FIFO的输出端子连接到下一级的上下复用器。 每个多路复用器的一个输出端连接到基数-4分支度量计算器。 因此，可以通过使用与输入I和Q位流的时钟速度相同的时钟来实现基数-4分支度量计算。 该结构和该方法可以应用于从½码导出的所有穿孔码的基数-4分支度量计算的解穿孔过程。

公开(公告)号：US20070130598A1

公开(公告)日：2007-06-07

申请号：US11607637

申请日：2006-11-30

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh

IPC分类号： H04N7/173 ,  H04N7/18 ,  H04N7/16 ,  H04N7/20

CPC分类号： H04L12/2803 ,  H04B3/54 ,  H04B2203/5441 ,  H04B2203/5445 ,  H04L12/2801 ,  H04L12/2818 ,  H04L2012/2841 ,  H04L2012/2843 ,  H04N21/4131 ,  H04N21/4227 ,  H04N21/4355 ,  H04N21/43615 ,  H04N21/478 ,  H04N21/6143 ,  H04N21/6193 ,  H04N21/6547

摘要： Provided is a digital satellite broadcasting set-top box and a home network control system employing the same. The set-top box includes: a satellite signal receiving unit for receiving a satellite signal including a home network control signal for controlling the household appliances through a satellite broadcasting network from a remote terminal; and a control unit for extracting a household appliances control signal included in the satellite signal transmitted from the satellite signal receiving unit and commanding a power line converter to transmit the household appliances control signal to a corresponding household appliance, wherein the power line converter converts the household appliances control signal transmitted from the digital satellite broadcasting set-top box into a power line communication signal and transmits the power line communication signal on the home network through a power line.

摘要翻译： 提供了一种数字卫星广播机顶盒和采用其的家庭网络控制系统。 机顶盒包括：卫星信号接收单元，用于通过卫星广播网络从远程终端接收包括用于控制家用电器的家庭网络控制信号的卫星信号; 以及控制单元，用于提取从卫星信号接收单元发送的卫星信号中包含的家用电器控制信号，并指示电力线转换器将家用电器控制信号发送到相应的家用电器，其中电力线转换器将家庭 家用电器控制信号从数字卫星广播机顶盒发送到电力线通信信号，并通过电力线在家庭网络上发送电力线通信信号。

公开(公告)号：US20050144543A1

公开(公告)日：2005-06-30

申请号：US10888167

申请日：2004-07-09

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Ji-Won Jung ,  Sung-Jun Cho ,  Tae-Gil Lee ,  Sang-Jin Park ,  In-Ki Lee

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Ji-Won Jung ,  Sung-Jun Cho ,  Tae-Gil Lee ,  Sang-Jin Park ,  In-Ki Lee

IPC分类号： G06F11/00

CPC分类号： H04L1/0057 ,  H03M13/1105 ,  H03M13/6337 ,  H03M13/6594 ,  H04L2001/0093

摘要： The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (σ) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.

摘要翻译： 本发明涉及使用信道可靠性值和低密度奇偶校验（LDPC）解码系统的非均匀量化的预处理装置。 预处理装置可以呈现性能下降，并且通过基于信道可靠性值的非均匀量化来估计离散信道可靠性值（L> c * *）来执行解码预处理 通过预先执行的模拟估计的误码率（BER）与噪声估计误差和p的预定范围内的信道噪声的标准偏差（sigma）之间的关系，以及将接收信号与离散信道 可靠性值。 预处理装置包括：信道可靠性测量单元，不均匀量化单元，符号位加法单元，位移单元。

公开(公告)号：US07325174B2

公开(公告)日：2008-01-29

申请号：US10888167

申请日：2004-07-09

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Ji-Won Jung ,  Sung-Jun Cho ,  Tae-Gil Lee ,  Sang-Jin Park ,  In-Ki Lee

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Ji-Won Jung ,  Sung-Jun Cho ,  Tae-Gil Lee ,  Sang-Jin Park ,  In-Ki Lee

IPC分类号： G06F11/00

CPC分类号： H04L1/0057 ,  H03M13/1105 ,  H03M13/6337 ,  H03M13/6594 ,  H04L2001/0093

摘要： The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (σ) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.

摘要翻译： 本发明涉及使用信道可靠性值和低密度奇偶校验（LDPC）解码系统的非均匀量化的预处理装置。 预处理装置可以呈现性能下降，并且通过基于信道可靠性值的非均匀量化来估计离散信道可靠性值（L> c * *）来执行解码预处理 通过预先执行的模拟估计的误码率（BER）与噪声估计误差和p的预定范围内的信道噪声的标准偏差（sigma）之间的关系，以及将接收信号与离散信道 可靠性值。 预处理装置包括：信道可靠性测量单元，不均匀量化单元，符号位加法单元，位移单元。

公开(公告)号：US20050141409A1

公开(公告)日：2005-06-30

申请号：US10934000

申请日：2004-09-03

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Ji-Won Jung

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Ji-Won Jung

IPC分类号： H03M13/37 ,  H04J11/00 ,  H04L1/00 ,  H04L27/18

CPC分类号： H04L1/005 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0071 ,  H04L27/186

摘要： A turbo TCM decoder for performing a soft decision without performing a sector phase quantization is disclosed. The turbo TCM decoder includes: a symbol transformer for converting a received signal to signal bits of QPSK mode by using an I-axis coordinate and a Q-axis coordinate on a constellation of the received signal; a phase sector quantizer for performing a phase sector quantization or the received signal by using the I-axis coordinate and the Q-axis coordinate; a first decoder for determining coded data by decoding the converted signal bits; a delay for delaying the quantized signal; and a second decoder for determining un-coded data by using the delayed quantized signal and the determined coded data.

摘要翻译： 公开了一种用于在不执行扇区相位量化的情况下执行软判决的turbo TCM解码器。 涡轮TCM解码器包括：符号变换器，用于通过使用接收信号的星座上的I轴坐标和Q轴坐标将接收信号转换为QPSK模式的信号位; 相位扇区量化器，用于通过使用I轴坐标和Q轴坐标来执行相位扇区量化或接收信号; 第一解码器，用于通过解码转换的信号位来确定编码数据; 用于延迟量化信号的延迟; 以及第二解码器，用于通过使用延迟量化信号和所确定的编码数据来确定未编码数据。

公开(公告)号：US07613103B2

公开(公告)日：2009-11-03

申请号：US10934000

申请日：2004-09-03

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Ji-Won Jung

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Ji-Won Jung

IPC分类号： H04J11/00

CPC分类号： H04L1/005 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0071 ,  H04L27/186

摘要： A turbo TCM decoder for performing a soft decision without performing a sector phase quantization is disclosed. The turbo TCM decoder includes: a symbol transformer for converting a received signal to signal bits of QPSK mode by using an I-axis coordinate and a Q-axis coordinate on a constellation of the received signal; a phase sector quantizer for performing a phase sector quantization or the received signal by using the I-axis coordinate and the Q-axis coordinate; a first decoder for determining coded data by decoding the converted signal bits; a delay for delaying the quantized signal; and a second decoder for determining un-coded data by using the delayed quantized signal and the determined coded data.

摘要翻译： 公开了一种用于在不执行扇区相位量化的情况下执行软判决的turbo TCM解码器。 涡轮TCM解码器包括：符号变换器，用于通过使用接收信号的星座上的I轴坐标和Q轴坐标将接收信号转换为QPSK模式的信号位; 相位扇区量化器，用于通过使用I轴坐标和Q轴坐标来执行相位扇区量化或接收信号; 第一解码器，用于通过解码转换的信号位来确定编码数据; 用于延迟量化信号的延迟; 以及第二解码器，用于通过使用延迟量化信号和所确定的编码数据来确定未编码数据。

公开(公告)号：US20070150789A1

公开(公告)日：2007-06-28

申请号：US11607592

申请日：2006-11-30

申请人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/1111

摘要： Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

摘要翻译： 提供了一种使用类型分类索引的低密度奇偶校验（LDPC）解码装置和方法。 该装置包括：存储器分配单元，用于将接收数据乘以估计的信道值，并将乘法值存储在包括多个存储块的存储器中; 索引存储单元，用于存储所存储的数据的只读存储器（ROM）索引，地址索引和置换索引; 检查节点更新单元，用于基于所述ROM索引，所述地址索引和所述置换索引并行存储所述数据，并更新校验节点; 以及位节点更新单元，用于基于存储在存储器中的数据更新位节点，并且校验在校验节点更新单元中更新的节点信息。

公开(公告)号：US08122315B2

公开(公告)日：2012-02-21

申请号：US11607592

申请日：2006-11-30

申请人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/1111

摘要： Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

摘要翻译： 提供了一种使用类型分类索引的低密度奇偶校验（LDPC）解码装置和方法。 该装置包括：存储器分配单元，用于将接收数据乘以估计的信道值，并将乘法值存储在包括多个存储块的存储器中; 索引存储单元，用于存储所存储的数据的只读存储器（ROM）索引，地址索引和置换索引; 检查节点更新单元，用于基于所述ROM索引，所述地址索引和所述置换索引并行存储所述数据，并更新校验节点; 以及位节点更新单元，用于基于存储在存储器中的数据更新位节点，并且校验在校验节点更新单元中更新的节点信息。