公开(公告)号：US09575125B1

公开(公告)日：2017-02-21

申请号：US14049543

申请日：2013-10-09

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  William Meadows

IPC: G01R31/3193 ,  G11C29/10

CPC classification number: G01R31/3193 ,  G01R31/31718 ,  G11C29/10 ,  G11C29/42 ,  G11C29/52

Abstract: In some examples, a memory device generates and exposes parity/difference information to a test system to reduce overall test time. The parity/difference information may be generated based on parity bits read from the memory device and parity bits produced from data bits stored in the memory device. In some cases, the parity/difference information may be compared to an expected parity/difference to determine a number of correctable errors which occurred during testing, while the data bits may be compared to expected data to determine a number of uncorrectable errors which occurred during testing.

Abstract translation: 在一些示例中，存储器件生成并将奇偶校验/差异信息暴露给测试系统以减少总体测试时间。 可以基于从存储器件读取的奇偶校验位和从存储在存储器件中的数据位产生的校验位来生成校验/差分信息。 在某些情况下，可以将奇偶校验/差分信息与期望的奇偶校验/差异进行比较，以确定在测试期间发生的可校正错误的数量，同时可将数据比特与期望数据进行比较，以确定在期间发生的不可校正错误的数量 测试。