公开(公告)号：US20170373008A1

公开(公告)日：2017-12-28

申请号：US15676360

申请日：2017-08-14

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION

Inventor： John CONSTANTINO ,  Timwah LUK ,  Ahmad ASHRAFZADEH ,  Robert L. KRAUSE ,  Etan SHACHAM ,  Maria Clemens Ypil QUINONES ,  Janusz BRYZEK ,  Chung-Lin WU

IPC: H01L23/538 ,  H01L49/02 ,  H01L27/06 ,  H01L23/495 ,  H01L23/66

CPC classification number: H01L23/538 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/642 ,  H01L23/66 ,  H01L27/06 ,  H01L28/40 ,  H01L2223/6655 ,  H01L2224/0603 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

公开(公告)号：US20150200162A1

公开(公告)日：2015-07-16

申请号：US14593642

申请日：2015-01-09

Applicant: Fairchild Semiconductor Corporation

Inventor： John CONSTANTINO ,  Timwah LUK ,  Ahmad ASHRAFZADEH ,  Robert L. KRAUSE ,  Etan SHACHAM ,  Maria Clemens Ypil QUINONES ,  Janusz BRYZEK ,  Chung-Lin WU

IPC: H01L23/538 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/538 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/66 ,  H01L27/06 ,  H01L28/40 ,  H01L2224/0603 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Abstract translation: 在一些一般方面，装置可以包括耦合到第一半导体管芯和第二半导体管芯的第一半导体管芯，第二半导体管芯和电容隔离电路。 电容隔离电路可以设置在第一半导体管芯和第二半导体管芯的外侧。 第一半导体管芯，第二半导体管芯和电容电路可以包括在半导体封装的模制中。