公开(公告)号：US20170279644A1

公开(公告)日：2017-09-28

申请号：US15241618

申请日：2016-08-19

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yuan-Min Hu ,  Jhen-Yu Hou

IPC: H04L27/00

CPC classification number: H04L27/0014 ,  H03K3/00 ,  H03K5/1252 ,  H03L7/00 ,  H03L7/08 ,  H04J3/04 ,  H04L2027/0036

Abstract: A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.

公开(公告)号：US09806923B2

公开(公告)日：2017-10-31

申请号：US15241618

申请日：2016-08-19

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yuan-Min Hu ,  Jhen-Yu Hou

IPC: H04L7/00 ,  H03D3/24 ,  H04L27/00 ,  H03K3/00 ,  H03L7/00 ,  H03L7/08

CPC classification number: H04L27/0014 ,  H03K3/00 ,  H03K5/1252 ,  H03L7/00 ,  H03L7/08 ,  H04J3/04 ,  H04L2027/0036

Abstract: A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.