公开(公告)号：US10320185B2

公开(公告)日：2019-06-11

申请号：US15273223

申请日：2016-09-22

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Robert Matthew Mertens ,  Alexander Paul Gerdemann ,  Michael A. Stockinger

IPC分类号： H02H9/00 ,  H02H9/04 ,  H03K17/0812 ,  H01L27/02 ,  H02H3/22

摘要： An integrated circuit for protecting against transient electrical stress events includes a rail clamp device, and a trigger circuit including a resistive-capacitive (RC) filter, a drive circuit including a first inverter stage receiving an input signal from the RC filter, the drive circuit is configured to enable the rail clamp device during a transient electrical stress event, and a stress event detection circuit coupled to the RC filter. The drive circuit includes a configurable activation voltage which is controlled by the stress event detection circuit, wherein the activation voltage is reduced when the transient electrical stress event is detected.

公开(公告)号：US20160294378A1

公开(公告)日：2016-10-06

申请号：US14887271

申请日：2015-10-19

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Wenzhong Zhang ,  Michael A. Stockinger

IPC分类号： H03K17/081 ,  H03K19/0185 ,  H03K5/08

CPC分类号： H03K19/018521 ,  H03K5/08

摘要： A transmission gate circuit includes a pass gate and a control circuit and provides High Voltage protection to a flash memory in a characterization mode and a low resistive path with true open-drain functionality in a normal mode. A native NMOSFET in series with the pass gate provides overvoltage protection for additional circuitry. Well biasing, gate tracking and internal node clamping circuits ensure that all of the devices of the pass gate and control circuit operated within safe operational voltage levels. The two modes of operation can be selected by an enable signal. The transmission gate circuit can support up to a 5.5 volts input in a true open drain mode while an input/output supply voltage of 3.3 volts is supplied.

摘要翻译： 传输门电路包括通过栅极和控制电路，并在正常模式下以表征模式和具有真实漏极开路功能的低电阻路径向快闪存储器提供高电压保护。 与通过栅极串联的天然NMOSFET为额外的电路提供过压保护。 良好的偏置，栅极跟踪和内部节点钳位电路确保通过栅极和控制电路的所有器件在安全的工作电压水平下运行。 这两种工作模式可以通过使能信号来选择。 传输门电路可以以真正的开漏模式支持高达5.5伏的输入，同时提供3.3伏特的输入/输出电源电压。

公开(公告)号：US20140327079A1

公开(公告)日：2014-11-06

申请号：US13875618

申请日：2013-05-02

申请人： Freescale Semiconductor, Inc.

发明人： Melanie Etherton ,  Alex P. Gerdemann ,  James W. Miller ,  Mohamed S. Moosa ,  Robert S. Ruth ,  Michael A. Stockinger

IPC分类号： H01L27/02

CPC分类号： H01L27/0292 ,  H01L27/0285

摘要： Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.

摘要翻译： 具有高有效保持电压的增压静电放电（ESD）钳位电路。 在一些实施例中，集成电路可以包括可操作地耦合到第一电压总线和参考总线的触发电路; 二极管，包括可操作地耦合到第二电压总线的阳极端子，所述第二电压母线与所述第一电压总线不同; 晶体管，其包括可操作地耦合到触发电路的输出端的栅极，可操作地耦合到二极管的阴极端子的漏极和可操作地耦合到参考总线的源极; 以及可操作地耦合到第一电压总线，第二电压总线和参考总线的输入/输出（I / O）单元。

公开(公告)号：US10164426B2

公开(公告)日：2018-12-25

申请号：US15166683

申请日：2016-05-27

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Michael A. Stockinger ,  Gregory C. Edgington ,  James R. Feddeler ,  Xiang Li ,  Richard W. Moseley ,  Mihir Suchak

IPC分类号： H02H9/00 ,  H02H9/04 ,  H02H1/00 ,  G01R31/28 ,  H01L21/66 ,  G01R31/00 ,  H01L27/02

摘要： An integrated circuit includes an I/O pad and a protection device coupled to the I/O pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. An event level sensor includes a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to the protection device, and a second current electrode coupled to a load circuit; a rectifier device coupled between the second current electrode and a capacitor; a second transistor having a control electrode coupled to the capacitor; and an output circuit configured to place a current on a first sense bus proportional to a current through the load circuit.

公开(公告)号：US10074643B2

公开(公告)日：2018-09-11

申请号：US15273220

申请日：2016-09-22

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Robert Matthew Mertens ,  Michael A. Stockinger ,  Alexander Paul Gerdemann

IPC分类号： H01L27/02 ,  H03K19/20 ,  H01L23/60 ,  H02H9/04

CPC分类号： H01L27/0248 ,  H01L23/60 ,  H01L27/0285 ,  H02H9/046 ,  H03K19/20

摘要： An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.

公开(公告)号：US09076656B2

公开(公告)日：2015-07-07

申请号：US13875618

申请日：2013-05-02

申请人： Freescale Semiconductor, Inc.

发明人： Melanie Etherton ,  Alex P. Gerdemann ,  James W. Miller ,  Mohamed S. Moosa ,  Robert S. Ruth ,  Michael A. Stockinger

IPC分类号： H01L27/02

CPC分类号： H01L27/0292 ,  H01L27/0285

摘要： Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.

摘要翻译： 具有高有效保持电压的增压静电放电（ESD）钳位电路。 在一些实施例中，集成电路可以包括可操作地耦合到第一电压总线和参考总线的触发电路; 二极管，包括可操作地耦合到第二电压总线的阳极端子，所述第二电压母线与所述第一电压总线不同; 晶体管，其包括可操作地耦合到触发电路的输出端的栅极，可操作地耦合到二极管的阴极端子的漏极和可操作地耦合到参考总线的源极; 以及可操作地耦合到第一电压总线，第二电压总线和参考总线的输入/输出（I / O）单元。

公开(公告)号：US09941883B2

公开(公告)日：2018-04-10

申请号：US14887271

申请日：2015-10-19

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Wenzhong Zhang ,  Michael A. Stockinger

IPC分类号： H03K19/0185 ,  H03K5/08

CPC分类号： H03K19/018521 ,  H03K5/08

摘要： A transmission gate circuit includes a pass gate and a control circuit and provides High Voltage protection to a flash memory in a characterization mode and a low resistive path with true open-drain functionality in a normal mode. A native NMOSFET in series with the pass gate provides overvoltage protection for additional circuitry. Well biasing, gate tracking and internal node clamping circuits ensure that all of the devices of the pass gate and control circuit operated within safe operational voltage levels. The two modes of operation can be selected by an enable signal. The transmission gate circuit can support up to a 5.5 volts input in a true open drain mode while an input/output supply voltage of 3.3 volts is supplied.

公开(公告)号：US09553446B2

公开(公告)日：2017-01-24

申请号：US14529282

申请日：2014-10-31

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Alex P. Gerdemann ,  Melanie Etherton ,  James W. Miller ,  Mohamed S. Moosa ,  Robert S. Ruth ,  Michael A. Stockinger

IPC分类号： H02H9/00 ,  H02H9/04

CPC分类号： H02H9/046

摘要： An integrated circuit including ESD circuitry that is shared among more than one terminal segment of the integrated circuit to discharge current from an ESD event on any of the terminal segments. The shared ESD circuitry includes a clamp circuit that is coupled to power buses of each segment to discharge current from ESD events on each segment. The shared ESD circuitry includes a trigger circuit that is coupled to nodes coupled to terminals of each segment to detect an ESD event on each segment.

摘要翻译： 一种集成电路，其包括在集成电路的多于一个端子段之间共享的ESD电路，以从任何终端段上的ESD事件放电电流。 共享ESD电路包括钳位电路，其被耦合到每个段的电源总线以从每个段上的ESD事件放电电流。 共享ESD电路包括触发电路，其耦合到耦合到每个段的终端的节点，以检测每个段上的ESD事件。