公开(公告)号：US20050246507A1

公开(公告)日：2005-11-03

申请号：US10834637

申请日：2004-04-29

申请人： Fadi Busaba ,  Steven Carlough ,  Mark Check ,  Christopher Krygowski ,  John Rell ,  Frank Tanzi

发明人： Fadi Busaba ,  Steven Carlough ,  Mark Check ,  Christopher Krygowski ,  John Rell ,  Frank Tanzi

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3824 ,  G06F12/0886

摘要： A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.

摘要翻译： 在指令执行期间预先对准用于存储的数据的方法通过消除数据对准所需的周期来提高性能。 该方法可以在ASCII和Packed Decimal格式之间以及Unicode Basic Latin和Packed Decimal格式之间转换数据。 转换为打包十进制硬件需要十进制格式，用于生成十进制结果的微处理器。 从包装十进制转换为ASCII和Unicode基本拉丁文需要以应用程序所需的格式报告十进制算术结果。 为了进一步提高性能，利用固定点单元（FXU）中的所有可用写入端口来减少存储结果所需的周期数。 为了防止数据获取未使用的目标数据缓慢的指令执行，目标位置被测试存储访问异常，但是这些操作数的数据实际上并没有被提取。 从FXU到操作数缓冲区的单个读取请求在单个周期中有效读取整个目标地址（最多8个双字的数据）。

公开(公告)号：US20070233773A1

公开(公告)日：2007-10-04

申请号：US11749224

申请日：2007-05-16

申请人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

发明人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

IPC分类号： G06F7/44

CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.

摘要翻译： 超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

公开(公告)号：US20060259530A1

公开(公告)日：2006-11-16

申请号：US11460296

申请日：2006-07-27

申请人： Fadi Busaba ,  Steven Carlough ,  Christopher Krygowski ,  John Rell

发明人： Fadi Busaba ,  Steven Carlough ,  Christopher Krygowski ,  John Rell

IPC分类号： G06F7/38

CPC分类号： G06F9/3001 ,  G06F7/496

摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.

摘要翻译： 一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。 部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍 乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

公开(公告)号：US20070214205A1

公开(公告)日：2007-09-13

申请号：US11749239

申请日：2007-05-16

申请人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

发明人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

IPC分类号： G06F7/52

CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.

摘要翻译： 在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

公开(公告)号：US20120117427A1

公开(公告)日：2012-05-10

申请号：US12942036

申请日：2010-11-09

申请人： Eli Almog ,  Oz Dov Hershkovitz ,  Christopher Krygowski

发明人： Eli Almog ,  Oz Dov Hershkovitz ,  Christopher Krygowski

IPC分类号： G06F11/26

CPC分类号： G06F11/263 ,  G06F11/261

摘要： Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a “rollover mode”. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite.

摘要翻译： 公开了支持运行自修改代码的功能的被测系统（SUT）的验证。 发生器可以生成自修改代码。 响应于模拟器将要模拟由自修改代码生成的代码的识别，模拟器可以以“翻转模式”模拟执行。 代码可以包括具有可变字节大小，分支指令，循环等的指令代码。 模拟器可以进一步模拟无效指令的执行。 在某些情况下，模拟器可以执行回滚模拟翻转模式，并避免进入翻转模式。 响应于识别终止条件，模拟器可以执行回滚，以确保避免无尽循环。 响应于读取不确定的初始化值，模拟器可以执行回滚。

公开(公告)号：US08707101B2

公开(公告)日：2014-04-22

申请号：US12942036

申请日：2010-11-09

申请人： Eli Almog ,  Oz Dov Hershkovitz ,  Christopher Krygowski

发明人： Eli Almog ,  Oz Dov Hershkovitz ,  Christopher Krygowski

IPC分类号： G06F11/00

CPC分类号： G06F11/263 ,  G06F11/261

摘要： Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a “rollover mode”. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite.

摘要翻译： 公开了支持运行自修改代码的功能的被测系统（SUT）的验证。 发生器可以生成自修改代码。 响应于模拟器将要模拟由自修改代码生成的代码的识别，模拟器可以以“翻转模式”模拟执行。 代码可以包括具有可变字节大小，分支指令，循环等的指令代码。 模拟器可以进一步模拟无效指令的执行。 在某些情况下，模拟器可以执行回滚模拟翻转模式，并避免进入翻转模式。 响应于识别终止条件，模拟器可以执行回滚，以确保避免无尽循环。 响应于读取不确定的初始化值，模拟器可以执行回滚。