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    Instruction cracking based on machine state
    1.
    发明授权
    Instruction cracking based on machine state 有权
    基于机器状态的指令开裂

    公开(公告)号：US08938605B2

    公开(公告)日：2015-01-20

    申请号：US12718685

    申请日：2010-03-05

    申请人： Fadi Busaba ,  Bruce Giamei ,  David Hutton ,  Eric Schwarz

    发明人： Fadi Busaba ,  Bruce Giamei ,  David Hutton ,  Eric Schwarz

    IPC分类号： G06F9/30 ,  G06F9/34

    CPC分类号： G06F9/342 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30189

    摘要： A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.

    摘要翻译： 一种基于机器状态的方法，信息处理系统和计算机程序产品管理指令执行。 至少接收一条指令。 至少一条指令被解码。 响应于解码确定当前机器状态。 基于已经确定的当前机器状态将至少一个指令组织成一组操作单元。 执行一组操作单元。

    INSTRUCTION CRACKING AND ISSUE SHORTENING BASED ON INSTRUCTION BASE FIELDS, INDEX FIELDS, OPERAND FIELDS, AND VARIOUS OTHER INSTRUCTION TEXT BITS
    3.
    发明申请
    INSTRUCTION CRACKING AND ISSUE SHORTENING BASED ON INSTRUCTION BASE FIELDS, INDEX FIELDS, OPERAND FIELDS, AND VARIOUS OTHER INSTRUCTION TEXT BITS 有权
    基于指示基地字段，索引字段，操作字段以及各种其他指令文本位置的指令性破解和问题解决

    公开(公告)号：US20110252220A1

    公开(公告)日：2011-10-13

    申请号：US12757330

    申请日：2010-04-09

    申请人： Fadi BUSABA ,  Brian CURRAN ,  Lee EISEN ,  Bruce GIAMEI ,  David HUTTON

    发明人： Fadi BUSABA ,  Brian CURRAN ,  Lee EISEN ,  Bruce GIAMEI ,  David HUTTON

    IPC分类号： G06F9/44 ,  G06F9/30

    CPC分类号： G06F9/3017 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30058

    摘要： A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品破解和/或缩短计算机可执行指令。 至少接收一条指令。 至少对指令进行分析。 识别与该至少一条指令相关联的指令类型。 分析指令的基本字段，索引字段，一个或多个操作数和掩码字段中的至少一个。 然后执行以下中的至少一个：将至少一个指令组织成一组操作单元; 并且至少一个指令被缩短。 然后执行一组操作单元。

    COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA
    4.
    发明申请
    COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA 失效
    收集计算机处理器仪表数据

    公开(公告)号：US20110154298A1

    公开(公告)日：2011-06-23

    申请号：US12645687

    申请日：2009-12-23

    申请人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

    发明人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

    IPC分类号： G06F9/44

    CPC分类号： G06F11/348 ,  G06F11/3409

    摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

    摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。

    History based line install
    7.
    发明申请
    History based line install 审中-公开
    基于历史的线路安装

    公开(公告)号：US20070180193A1

    公开(公告)日：2007-08-02

    申请号：US11342993

    申请日：2006-01-30

    申请人： David Hutton ,  Kathryn Jackson ,  Keith Langston ,  Pak-kin Mak ,  Arthur O'Neill

    发明人： David Hutton ,  Kathryn Jackson ,  Keith Langston ,  Pak-kin Mak ,  Arthur O'Neill

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0815 ,  G06F12/0811 ,  G06F2212/507

    摘要： Using local change bit to direct the install state of the data line. A multi-processor system that having a plurality of individual processors where each of the processors has an associated L1 cache, and the multi-processor system has at least one shared main memory, and at least one shared L2 cache. The method described herein involves writing a data line into an L2 cache comprising and a local change bit to direct the install state of the data line.

    摘要翻译： 使用本地更改位来指示数据行的安装状态。 一种具有多个单独处理器的多处理器系统，其中每个处理器具有相关联的L1高速缓存，并且多处理器系统具有至少一个共享主存储器和至少一个共享L2高速缓存。 这里描述的方法涉及将数据线写入L2缓存和本地改变位以指导数据线的安装状态。

    Separate data/coherency caches in a shared memory multiprocessor system
    8.
    发明申请
    Separate data/coherency caches in a shared memory multiprocessor system 有权
    在共享内存多处理器系统中分离数据/一致性高速缓存

    公开(公告)号：US20070168619A1

    公开(公告)日：2007-07-19

    申请号：US11334280

    申请日：2006-01-18

    申请人： David Hutton ,  Kathryn Jackson ,  Keith Langston ,  Pak-kin Mak ,  Bruce Wagar

    发明人： David Hutton ,  Kathryn Jackson ,  Keith Langston ,  Pak-kin Mak ,  Bruce Wagar

    IPC分类号： G06F13/28 ,  G06F12/00

    CPC分类号： G06F12/0824

    摘要： The system and method described herein is a dual system directory structure that performs the role of system cache, i.e., data, and system control, i.e., coherency. The system includes two system cache directories. These two cache directories are equal in size and collectively large enough to contain all of the processor cache directory entries, but with only one of these cache directories hosting system-cache data to back the most recent fraction of data accessed by the processors, and the other cache directory retains only addreses, including addresses of lines LRUed out and the processor using the data. By this expedient, only the directory known to be backed by system cached data will be evaluated for system cache data hits.

    摘要翻译： 这里描述的系统和方法是执行系统高速缓存（即数据）和系统控制（即一致性）的双重系统目录结构。 该系统包括两个系统缓存目录。 这两个缓存目录的大小相等，并且集体大到足以包含所有处理器高速缓存目录条目，但只有这些缓存目录中的一个托管系统高速缓存数据以支持由处理器访问的最近一小部分数据，而 其他缓存目录仅保留地址，包括LRUed out的行地址和使用该数据的处理器。 通过这种方式，只有系统缓存数据的已知备份的目录将被评估用于系统缓存数据命中。