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    DECIMAL MULTIPLICATION FOR SUPERSCALER PROCESSORS
    1.
    发明申请
    DECIMAL MULTIPLICATION FOR SUPERSCALER PROCESSORS 失效
    超级处理器的十进制多路复用

    公开(公告)号：US20060259530A1

    公开(公告)日：2006-11-16

    申请号：US11460296

    申请日：2006-07-27

    申请人： Fadi Busaba ,  Steven Carlough ,  Christopher Krygowski ,  John Rell

    发明人： Fadi Busaba ,  Steven Carlough ,  Christopher Krygowski ,  John Rell

    IPC分类号： G06F7/38

    CPC分类号： G06F9/3001 ,  G06F7/496

    摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.

    摘要翻译： 一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。 部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍 乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

    Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data
    2.
    发明申请
    Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data 有权
    用于打包十进制数据的存储预对齐和EBCDIC，ASCII和unicode基本拉丁转换

    公开(公告)号：US20050246507A1

    公开(公告)日：2005-11-03

    申请号：US10834637

    申请日：2004-04-29

    申请人： Fadi Busaba ,  Steven Carlough ,  Mark Check ,  Christopher Krygowski ,  John Rell ,  Frank Tanzi

    发明人： Fadi Busaba ,  Steven Carlough ,  Mark Check ,  Christopher Krygowski ,  John Rell ,  Frank Tanzi

    IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F12/00 ,  G06F12/08

    CPC分类号： G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3824 ,  G06F12/0886

    摘要： A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.

    摘要翻译： 在指令执行期间预先对准用于存储的数据的方法通过消除数据对准所需的周期来提高性能。 该方法可以在ASCII和Packed Decimal格式之间以及Unicode Basic Latin和Packed Decimal格式之间转换数据。 转换为打包十进制硬件需要十进制格式，用于生成十进制结果的微处理器。 从包装十进制转换为ASCII和Unicode基本拉丁文需要以应用程序所需的格式报告十进制算术结果。 为了进一步提高性能，利用固定点单元（FXU）中的所有可用写入端口来减少存储结果所需的周期数。 为了防止数据获取未使用的目标数据缓慢的指令执行，目标位置被测试存储访问异常，但是这些操作数的数据实际上并没有被提取。 从FXU到操作数缓冲区的单个读取请求在单个周期中有效读取整个目标地址（最多8个双字的数据）。

    MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS
    3.
    发明申请
    MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS 有权
    用于可变宽度的签名和不相关操作的模块化二进制多路复用器

    公开(公告)号：US20070233773A1

    公开(公告)日：2007-10-04

    申请号：US11749224

    申请日：2007-05-16

    申请人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

    发明人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

    IPC分类号： G06F7/44

    CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

    摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.

    摘要翻译： 超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

    MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS
    4.
    发明申请
    MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS 有权
    用于可变宽度的签名和不相关操作的模块化二进制多路复用器

    公开(公告)号：US20070214205A1

    公开(公告)日：2007-09-13

    申请号：US11749239

    申请日：2007-05-16

    申请人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

    发明人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

    摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.

    摘要翻译： 在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

    System and method for creating precise exceptions
    5.
    发明申请
    System and method for creating precise exceptions 失效
    用于创建精确异常的系统和方法

    公开(公告)号：US20060179290A1

    公开(公告)日：2006-08-10

    申请号：US11055193

    申请日：2005-02-10

    申请人： Fadi Busaba ,  Michael Mack ,  John Rell ,  Eric Schwarz ,  Chung-Lung Shum ,  Timothy Slegel ,  Scott Swaney ,  Sheryll Veneracion

    发明人： Fadi Busaba ,  Michael Mack ,  John Rell ,  Eric Schwarz ,  Chung-Lung Shum ,  Timothy Slegel ,  Scott Swaney ,  Sheryll Veneracion

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4812 ,  G06F9/30101 ,  G06F9/3863 ,  G06F2209/481

    摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.

    摘要翻译： 一种用于创建精确异常的方法，包括检查指向引起异常的指令。 检查点导致当前检查点状态。 当前检查点状态被锁定。 确定多个寄存器中的任一个是否需要恢复到当前检查点状态。 响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。 执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。

    Instruction length based cracking for instruction of variable length storage operands
    6.
    发明授权
    Instruction length based cracking for instruction of variable length storage operands 有权
    指令长度为可变长度存储操作数指令的破解

    公开(公告)号：US08495341B2

    公开(公告)日：2013-07-23

    申请号：US12707163

    申请日：2010-02-17

    申请人： Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi ,  Wen Li

    发明人： Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi ,  Wen Li

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30032 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3017

    摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。 接收至少一个可变操作数长度指令。 分析至少一个可变操作数长度指令。 基于分析来识别可变操作数长度指令中的至少一个操作数的长度。 所述至少一个可变操作数长度指令被组织成一组操作单元。 执行操作单元的集合。 所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。

    Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits
    8.
    发明授权
    Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits 有权
    基于指令字段，索引字段，操作数字段和各种其他指令文本位的指令破解和问题缩短

    公开(公告)号：US08464030B2

    公开(公告)日：2013-06-11

    申请号：US12757330

    申请日：2010-04-09

    申请人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Bruce Giamei ,  David Hutton

    发明人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Bruce Giamei ,  David Hutton

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F9/3017 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30058

    摘要： A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品破解和/或缩短计算机可执行指令。 至少接收一条指令。 至少对指令进行分析。 识别与该至少一条指令相关联的指令类型。 分析指令的基本字段，索引字段，一个或多个操作数和掩码字段中的至少一个。 然后执行以下中的至少一个：将至少一个指令组织成一组操作单元; 并且至少一个指令被缩短。 然后执行一组操作单元。

    Reducing operand store compare penalties
    10.
    发明授权
    Reducing operand store compare penalties 有权

    公开(公告)号：US09626189B2

    公开(公告)日：2017-04-18

    申请号：US13524356

    申请日：2012-06-15

    申请人： Fadi Busaba ,  David Hutton ,  John G. Rell, Jr. ,  Chung-Lung K. Shum

    发明人： Fadi Busaba ,  David Hutton ,  John G. Rell, Jr. ,  Chung-Lung K. Shum

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3838 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3834

    摘要： Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.