公开(公告)号：US20190204368A1

公开(公告)日：2019-07-04

申请号：US15949044

申请日：2018-04-09

Applicant: Faraday Technology Corp.

Inventor： Tang-Long Chang ,  Chi-Sheng Liao ,  Jeng-Huang Wu

IPC: G01R21/133 ,  G05F3/16 ,  G06F1/26 ,  G06F13/40

CPC classification number: G01R21/133 ,  G05F3/16 ,  G06F1/266 ,  G06F13/4004

Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.

公开(公告)号：US20200035670A1

公开(公告)日：2020-01-30

申请号：US16153829

申请日：2018-10-08

Applicant: Faraday Technology Corp.

Inventor： Chia-Ku Tsai ,  Chi-Sheng Liao ,  Jeng-Huang Wu

IPC: H01L27/02 ,  H02H9/04

Abstract: A electrostatic discharge (ESD) protection apparatus for an integrated circuit (IC) is provided. A first electrostatic current rail and a second electrostatic current rail of the ESD protection apparatus do not directly connected to any bonding pad of the IC. The ESD protection apparatus further includes a clamp circuit and four ESD protection circuits. The clamp circuit is coupled between the first electrostatic current rail and the second electrostatic current rail. A first ESD protection circuit is coupled between the first electrostatic current rail and a signal pad of the IC. A second ESD protection circuit is coupled between the signal pad and the second electrostatic current rail. A third ESD protection circuit is coupled between a first power rail and the second electrostatic current rail. A fourth ESD protection circuit is coupled between the second electrostatic current rail and a second power rail.