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    Method of fabricating openings and contact holes
    1.
    发明授权
    Method of fabricating openings and contact holes 有权
    制造开口和接触孔的方法

    公开(公告)号：US08236702B2

    公开(公告)日：2012-08-07

    申请号：US12042340

    申请日：2008-03-05

    申请人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

    发明人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

    摘要： A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.

    摘要翻译： 提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的半导体衬底。 然后对电介质层和蚀刻停止层进行图案化以形成暴露半导体衬底的多个开口。 随后形成介电薄膜以覆盖电介质层，开口的侧壁和半导体衬底。 然后去除设置在电介质层和半导体衬底上的电介质薄膜，同时保留设置在侧壁上的电介质薄膜。

    Method of fabricating openings
    2.
    发明授权
    Method of fabricating openings 有权
    开口方法

    公开(公告)号：US08592322B2

    公开(公告)日：2013-11-26

    申请号：US13535370

    申请日：2012-06-28

    申请人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

    发明人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

    摘要： A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

    摘要翻译： 公开了一种制造开口的方法。 首先，提供其上具有自对准硅化物区域的半导体衬底。 蚀刻停止层和至少介电层从底部到顶部设置在半导体衬底上。 其次，对电介质层和蚀刻停止层进行图案化以在电介质层和蚀刻停止层中形成多个开口，使得开口露出自对准区域。 然后，形成覆盖电介质层的电介质薄膜，开口侧壁和自对准硅化物区域。 然后，去除设置在电介质层和自对准硅化物区域上的电介质薄膜。

    Opening structure for semiconductor device
    3.
    发明授权
    Opening structure for semiconductor device 有权
    半导体器件的开口结构

    公开(公告)号：US08461649B2

    公开(公告)日：2013-06-11

    申请号：US13234159

    申请日：2011-09-16

    申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

    发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

    IPC分类号： H01L29/78

    CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

    摘要： An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.

    摘要翻译： 公开了一种开口结构。 开口结构包括：半导体衬底; 设置在所述半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁; 覆盖每个开口的侧壁的至少一部分的电介质薄膜; 蚀刻停止层，设置在所述半导体衬底和所述电介质层之间并且部分地延伸到所述开口中以将所述电介质薄膜与所述半导体衬底隔离; 以及填充在开口中的金属层。

    METHOD OF FABRICATING OPENINGS
    4.
    发明申请
    METHOD OF FABRICATING OPENINGS 有权
    制作开口的方法

    公开(公告)号：US20120270403A1

    公开(公告)日：2012-10-25

    申请号：US13535370

    申请日：2012-06-28

    申请人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

    发明人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

    IPC分类号： H01L21/306

    CPC分类号： H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

    摘要： A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

    摘要翻译： 公开了一种制造开口的方法。 首先，提供其上具有自对准硅化物区域的半导体衬底。 蚀刻停止层和至少介电层从底部到顶部设置在半导体衬底上。 其次，对电介质层和蚀刻停止层进行图案化以在电介质层和蚀刻停止层中形成多个开口，使得开口露出自对准区域。 然后，形成覆盖电介质层的电介质薄膜，开口侧壁和自对准硅化物区域。 然后，去除设置在电介质层和自对准硅化物区域上的电介质薄膜。

    OPENING STRUCTURE
    6.
    发明申请
    OPENING STRUCTURE 有权
    开放式结构

    公开(公告)号：US20120001338A1

    公开(公告)日：2012-01-05

    申请号：US13234159

    申请日：2011-09-16

    申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

    发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

    IPC分类号： H01L23/48

    CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

    摘要： An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.

    摘要翻译： 公开了一种开口结构。 开口结构包括：半导体衬底; 设置在所述半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁; 覆盖每个开口的侧壁的至少一部分的电介质薄膜; 蚀刻停止层，设置在所述半导体衬底和所述电介质层之间并且部分地延伸到所述开口中以将所述电介质薄膜与所述半导体衬底隔离; 以及填充在开口中的金属层。

    METHOD OF FABRICATING OPENINGS AND CONTACT HOLES
    7.
    发明申请
    METHOD OF FABRICATING OPENINGS AND CONTACT HOLES 有权
    制作开口和接触孔的方法

    公开(公告)号：US20080153295A1

    公开(公告)日：2008-06-26

    申请号：US12042340

    申请日：2008-03-05

    申请人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

    发明人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

    IPC分类号： H01L21/768 ,  H01L21/311

    CPC分类号： H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

    摘要： A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.

    摘要翻译： 提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的半导体衬底。 然后对电介质层和蚀刻停止层进行构图以形成暴露半导体衬底的多个开口。 随后形成介电薄膜以覆盖电介质层，开口的侧壁和半导体衬底。 然后去除设置在电介质层和半导体衬底上的电介质薄膜，同时保留设置在侧壁上的电介质薄膜。

    Mark structure and method for measuring alignment accuracy between former layer and latter layer
    9.
    发明授权
    Mark structure and method for measuring alignment accuracy between former layer and latter layer 有权
    用于测量前层和后层之间的对准精度的标记结构和方法

    公开(公告)号：US08546962B2

    公开(公告)日：2013-10-01

    申请号：US13042721

    申请日：2011-03-08

    申请人： Jun-Chi Huang ,  Po-Chao Tsao ,  Ming-Te Wei

    发明人： Jun-Chi Huang ,  Po-Chao Tsao ,  Ming-Te Wei

    IPC分类号： H01L23/544 ,  G01B15/00 ,  H01J37/00 ,  G01N23/225

    CPC分类号： G03F7/70633 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A mark structure for measuring the alignment accuracy between a former layer and a latter layer with electron beam inspection (EBI) is described. The mark structure includes multiple divisions, each of which includes at least one region that includes multiple parts each disposed with a pair of a pattern of the former layer and a pattern of the latter layer. In each region, all of the parts have the same distance in a direction between the pattern of the former layer and the pattern of the latter layer. The distance in the direction is varied over the regions of the divisions of the mark structure.

    摘要翻译： 描述了用电子束检查（EBI）测量前一层和后一层之间的对准精度的标记结构。 标记结构包括多个分割，每个分割部分包括至少一个区域，该区域包括多个部分，每个部分设置有前一层的一对图案和后一层的图案。 在每个区域中，所有部分在前一层的图案和后一层的图案之间的方向上具有相同的距离。 方向上的距离在标记结构的分割区域之间变化。