公开(公告)号：US4631667A

公开(公告)日：1986-12-23

申请号：US507854

申请日：1983-06-27

申请人： Ferruccio Zulian ,  Vittorio Zanchi

发明人： Ferruccio Zulian ,  Vittorio Zanchi

IPC分类号： G06F9/22 ,  G06F9/24 ,  G06F9/445 ,  G06F9/52 ,  G06F13/18 ,  G06F15/16 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F9/24 ,  G06F13/18

摘要： An asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus. Microinstructions are read out from working memory. At least one of the processors, in addition to conventional bus interface registers for latching of data, address and commands to be forwarded to the working memory through the bus, is provided with an additional interface register, devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. The system is further provided with a multiplexer for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus, via a direct path established between the system common bus and an input set of the multiplexer. The microinstruction transfer speed from working memory to the processor is further enhanced by means of different timing for the data transfer through the bus and the microinstruction transfer through the bus. In the case of data transfer a bus access cycle is started at the end of the processor cycle during which the relevant bus interface register is loaded. In the case of microinstruction read out from working memory, the additional interface register is loaded at the beginning of a processor cycle concurrently with the request of bus access cycle, so that the two overlap.

摘要翻译： 一种异步总线多处理器系统，其中多个微程序处理器通过公共总线与工作存储器通信。 微指令从工作记忆中读出。 除了用于锁存数据的常规总线接口寄存器，通过总线转发到工作存储器的地址和命令之外，至少一个处理器还具有附加的接口寄存器，专用于锁存微指令地址 从工作记忆中读出的微指令。 该系统还设置有多路复用器，用于经由建立在系统公共总线和多路复用器的输入集之间的直接路径从微程序控制存储器或从系统公共总线选择性地加载微指令寄存器。 通过对通过总线的数据传输和通过总线的微指令传输的不同时序，进一步增强了从工作存储器到处理器的微指令传送速度。 在数据传输的情况下，总线访问周期在加载相关总线接口寄存器的处理器周期结束时开始。 在从工作存储器读出微指令的情况下，附加接口寄存器在处理器周期开始时与总线访问周期的请求同时加载，使得两者重叠。

公开(公告)号：US4302808A

公开(公告)日：1981-11-24

申请号：US90616

申请日：1979-11-02

申请人： Vittorio Zanchi ,  Tiziano Maccianti

发明人： Vittorio Zanchi ,  Tiziano Maccianti

IPC分类号： G06F13/362 ,  G06F9/46 ,  G06F13/18 ,  G06F13/26 ,  G06F3/04

CPC分类号： G06F13/26 ,  G06F13/18

摘要： An interrupt handling apparatus for a data processing system comprising a plurality of processing units and a working memory to which the units may access through a common bus by means of multilevel priority or access requests.Access requests are forwarded by each unit to a bus access controller preferably made part of the working memory through a single lead for each unit, irrespective of the access request priority level; and if the priority level of an access request is high, a high priority level access request signal is distributed by the high priority level interrupting unit to the other system units, which mask their possible access request of a lower priority level in response to such signal.The bus access controller grants access to a unit at a time on a priority basis determined by a priority network in the controller totally insensitive to any priority level difference of the access requests.

摘要翻译： 一种用于数据处理系统的中断处理装置，包括多个处理单元和工作存储器，所述单元可通过多级优先级或访问请求通过公共总线访问。 访问请求由每个单元转发到总线访问控制器，优选地通过用于每个单元的单个引线作为工作存储器的一部分，而不考虑访问请求优先级; 并且如果访问请求的优先级高，则高优先级级别的访问请求信号由高优先级级别中断单元分配给其他系统单元，这些系统单元响应于这种信号屏蔽其较低优先级的可能的访问请求 。 总线访问控制器在优先级基础上一次授权对一个单元进行访问，该优先级由控制器中的优先级网络确定，对访问请求的任何优先级别差异完全不敏感。

公开(公告)号：US4365291A

公开(公告)日：1982-12-21

申请号：US35861

申请日：1979-05-03

申请人： Vittorio Zanchi ,  Tiziano Maccianti

发明人： Vittorio Zanchi ,  Tiziano Maccianti

IPC分类号： G06F13/18 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4239 ,  G06F13/18

摘要： A system comprising interface circuits for coupling together for bidirectional information communication the various units of a data processing system, wherein such communication is effected by a totally interlocked bidirectional dialogue carried out over a single lead, but utilizing signals transmitted on another lead of the interface for clearing the interface circuits associated with the single lead.

摘要翻译： 一种包括用于耦合在一起用于双向信息通信数据处理系统的各种单元的接口电路的系统，其中这种通信是通过在单个引线上执行的完全互锁的双向对话实现的，但是利用在该接口的另一个引线上传输的信号 清除与单个引线相关的接口电路。

公开(公告)号：US4429361A

公开(公告)日：1984-01-31

申请号：US271167

申请日：1981-06-08

申请人： Tiziano Maccianti ,  Vittorio Zanchi

发明人： Tiziano Maccianti ,  Vittorio Zanchi

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F9/268

摘要： Sequencer means for a microprogrammed control unit which develops consecutive addresses of microprograms, branches to subroutines with address saving and possible return to microprogram, as well as interrupting microprogram forcings with address saving of the interrupted microprograms.In order to allow the double saving of microprogram and subroutine addresses in case of concurrent interruptions and branches, the sequencer means is provided with two address generation loops each including a register. The two loops have a common portion to which they accede through a multiplexer. The first loop is further coupled to a saving register stack.While the first loop executes the saving of a microprogram address and the latching or a branch address received from the second loop, the second loop executes a first updating and related latching or interrupting microprogram address. During the following cycle, by command of the first microinstruction of the interrupting microprogram, the second loop performs a first updating and related latch of the interrupting microprogram address and the first loop saves into the register stack the branch address and performs a second updating and related latching of the interrupting microprogram address.

摘要翻译： 序列发生器用于微程序控制单元，该微控制单元产生微程序的连续地址，分支到具有地址节省和可能返回到微程序的子程序，以及中断微程序强制，具有中断的微程序的地址保存。 为了在并发中断和分支的情况下允许双重节省微程序和子程序地址，定序器装置设置有两个地址生成循环，每个循环包括一个寄存器。 两个回路具有通过多路复用器接入的公共部分。 第一个循环进一步耦合到保存寄存器堆栈。 当第一循环执行保存微程序地址和从第二循环接收的锁存或分支地址时，第二循环执行第一更新和相关的锁存或中断微程序地址。 在下一个周期中，通过命令中断微程序的第一次微指令，第二个循环执行中断微程序地址的第一次更新和相关锁存，第一个循环将寄存器堆栈保存到分支地址，并执行第二次更新和相关 中断微程序地址的锁存。