公开(公告)号：US4302808A

公开(公告)日：1981-11-24

申请号：US90616

申请日：1979-11-02

申请人： Vittorio Zanchi ,  Tiziano Maccianti

发明人： Vittorio Zanchi ,  Tiziano Maccianti

IPC分类号： G06F13/362 ,  G06F9/46 ,  G06F13/18 ,  G06F13/26 ,  G06F3/04

CPC分类号： G06F13/26 ,  G06F13/18

摘要： An interrupt handling apparatus for a data processing system comprising a plurality of processing units and a working memory to which the units may access through a common bus by means of multilevel priority or access requests.Access requests are forwarded by each unit to a bus access controller preferably made part of the working memory through a single lead for each unit, irrespective of the access request priority level; and if the priority level of an access request is high, a high priority level access request signal is distributed by the high priority level interrupting unit to the other system units, which mask their possible access request of a lower priority level in response to such signal.The bus access controller grants access to a unit at a time on a priority basis determined by a priority network in the controller totally insensitive to any priority level difference of the access requests.

摘要翻译： 一种用于数据处理系统的中断处理装置，包括多个处理单元和工作存储器，所述单元可通过多级优先级或访问请求通过公共总线访问。 访问请求由每个单元转发到总线访问控制器，优选地通过用于每个单元的单个引线作为工作存储器的一部分，而不考虑访问请求优先级; 并且如果访问请求的优先级高，则高优先级级别的访问请求信号由高优先级级别中断单元分配给其他系统单元，这些系统单元响应于这种信号屏蔽其较低优先级的可能的访问请求 。 总线访问控制器在优先级基础上一次授权对一个单元进行访问，该优先级由控制器中的优先级网络确定，对访问请求的任何优先级别差异完全不敏感。

公开(公告)号：US4429361A

公开(公告)日：1984-01-31

申请号：US271167

申请日：1981-06-08

申请人： Tiziano Maccianti ,  Vittorio Zanchi

发明人： Tiziano Maccianti ,  Vittorio Zanchi

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F9/268

摘要： Sequencer means for a microprogrammed control unit which develops consecutive addresses of microprograms, branches to subroutines with address saving and possible return to microprogram, as well as interrupting microprogram forcings with address saving of the interrupted microprograms.In order to allow the double saving of microprogram and subroutine addresses in case of concurrent interruptions and branches, the sequencer means is provided with two address generation loops each including a register. The two loops have a common portion to which they accede through a multiplexer. The first loop is further coupled to a saving register stack.While the first loop executes the saving of a microprogram address and the latching or a branch address received from the second loop, the second loop executes a first updating and related latching or interrupting microprogram address. During the following cycle, by command of the first microinstruction of the interrupting microprogram, the second loop performs a first updating and related latch of the interrupting microprogram address and the first loop saves into the register stack the branch address and performs a second updating and related latching of the interrupting microprogram address.

摘要翻译： 序列发生器用于微程序控制单元，该微控制单元产生微程序的连续地址，分支到具有地址节省和可能返回到微程序的子程序，以及中断微程序强制，具有中断的微程序的地址保存。 为了在并发中断和分支的情况下允许双重节省微程序和子程序地址，定序器装置设置有两个地址生成循环，每个循环包括一个寄存器。 两个回路具有通过多路复用器接入的公共部分。 第一个循环进一步耦合到保存寄存器堆栈。 当第一循环执行保存微程序地址和从第二循环接收的锁存或分支地址时，第二循环执行第一更新和相关的锁存或中断微程序地址。 在下一个周期中，通过命令中断微程序的第一次微指令，第二个循环执行中断微程序地址的第一次更新和相关锁存，第一个循环将寄存器堆栈保存到分支地址，并执行第二次更新和相关 中断微程序地址的锁存。

公开(公告)号：US5115498A

公开(公告)日：1992-05-19

申请号：US315996

申请日：1989-02-27

申请人： Tiziano Maccianti ,  Angelo Oldani

发明人： Tiziano Maccianti ,  Angelo Oldani

IPC分类号： G06F12/02

CPC分类号： G06F12/0284

摘要： A local memory fast selection apparatus is utilized in a data processing system having a plurality of memory resources including a local memory and addressing by logical/virtual addresses which are converted into physical addresses. The local memory fast selection apparatus comprises a memory management unit (MMU) for converting a logical address in a physical address and for generating a destination code which identifies the memory resource, and an auxiliary memory having the same number of addressable locations of the MMU and loaded together with the MMU. The auxiliary memory has a physical address corresponding to the logical address by which the MMU is addressed and a destination code. The auxiliary memory stores a bit decoded from the destination code and selects a predetermined memory resource. Thus, the auxiliary memory and the MMU can be read out together with the same logical address in order to jointly obtain a physical address from the MMU and a selection signal of the predetermined memory resource from the auxiliary memory without any delay caused by decoding operations.

公开(公告)号：US4661925A

公开(公告)日：1987-04-28

申请号：US550270

申请日：1983-11-09

申请人： Tiziano Maccianti ,  Flavio Balasini

发明人： Tiziano Maccianti ,  Flavio Balasini

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/46

CPC分类号： G06F9/30145 ,  G06F9/226 ,  G06F9/267 ,  G06F9/268 ,  G06F9/30167

摘要： Computer control memory apparatus is disclosed wherein the microinstructions may selectively have a variable bit length. A main control memory stores microinstructions having a basic length and they are read out and stored in a microinstruction register. Microinstruction prefixes are obtained from more than one source and are selectively added to the basic length microinstruction in the microinstruction register to create longer microinstructions, as needed, for controlling the operation of the computer. The microinstruction prefixes may be obtained from a secondary control memory that is addressed at the same time as the main control memory, or may be obtained from a field of N bits which is a part of a previous microinstruction read out of the main control memory and saved in an expansion register, or may be all zeroes when it is not desired to expand a microinstruction of basic length read out of the main control memory. All such microinstruction prefixes are connected via a multiplexer from their source to the portion of the microinstruction register used for prefixing them to the basic length microinstructions. In the event an interrupt occurs to obtain a higher priority string of microinstructions, the multiplexer is prevented from connecting the sources of microinstruction prefixes to the microinstruction register until the interrupt is ended.

摘要翻译： 公开了一种计算机控制存储装置，其中微指令可以选择性地具有可变位长度。 主控制存储器存储具有基本长度的微指令，并且它们被读出并存储在微指令寄存器中。 微指令前缀从多个源获得，并且被选择性地添加到微指令寄存器中的基本长度微指令，以根据需要创建更长的微指令，以控制计算机的操作。 微指令前缀可以从与主控制存储器同时寻址的辅助控制存储器获得，或者可以从作为从主控制存储器读出的先前微指令的一部分的N位的字段获得， 保存在扩展寄存器中，或者当不希望扩展从主控制存储器读出的基本长度的微指令时，可以全部为零。 所有这些微指令前缀通过多路复用器从其源连接到微指令寄存器的用于将它们前缀到基本长度微指令的部分。 在发生中断以获得较高优先级的微指令串的情况下，防止多路复用器将微指令前缀的源连接到微指令寄存器，直到中断结束。

公开(公告)号：US4849979A

公开(公告)日：1989-07-18

申请号：US93429

申请日：1987-09-04

申请人： Tiziano Maccianti ,  Luciano Raimondi

发明人： Tiziano Maccianti ,  Luciano Raimondi

IPC分类号： G06F11/16 ,  G06F11/267

CPC分类号： G06F11/1633 ,  G06F11/165 ,  G06F11/2215

摘要： A fault tolerant computer architecture in which a functional unit is duplicated and the input and output signals to and from the two units are compared with each other by comparators to provide an error signal in case of different behavior of the two units, resulting in different input/output signals. The operation of both functional units is controlled by a first read only control memory or alternatively by a second read/write control memory once it has been loaded with microprograms, under control of the first read only control memory. The correct behavior of the comparators is tested in a diagnostic mode by having one functional unit operated under control of the first memory and the other functional unit operated under control of the second memory, so that the two units are controlled to perform different functions which force the comparators to produce an error indication, the absence of which indicates that the comparators operation is faulty.

摘要翻译： 其中功能单元被复制的容错计算机架构以及来自两个单元的输入和输出信号通过比较器彼此比较，以在两个单元的不同行为的情况下提供误差信号，导致不同的输入 /输出信号。 在第一只读控制存储器的控制下，两个功能单元的操作由第一只读控制存储器控制，或者由第二读/写控制存储器控制，一旦其被加载微程序。 通过在第一存储器的控制下操作一个功能单元并且在第二存储器的控制下操作另一个功能单元，在诊断模式中测试比较器的正确行为，使得两个单元被控制以执行不同的功能，其强制 比较器产生错误指示，其中不存在表示比较器操作有故障。

公开(公告)号：US4365291A

公开(公告)日：1982-12-21

申请号：US35861

申请日：1979-05-03

申请人： Vittorio Zanchi ,  Tiziano Maccianti

发明人： Vittorio Zanchi ,  Tiziano Maccianti

IPC分类号： G06F13/18 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4239 ,  G06F13/18

摘要： A system comprising interface circuits for coupling together for bidirectional information communication the various units of a data processing system, wherein such communication is effected by a totally interlocked bidirectional dialogue carried out over a single lead, but utilizing signals transmitted on another lead of the interface for clearing the interface circuits associated with the single lead.

摘要翻译： 一种包括用于耦合在一起用于双向信息通信数据处理系统的各种单元的接口电路的系统，其中这种通信是通过在单个引线上执行的完全互锁的双向对话实现的，但是利用在该接口的另一个引线上传输的信号 清除与单个引线相关的接口电路。