公开(公告)号：US07533241B2

公开(公告)日：2009-05-12

申请号：US11634253

申请日：2006-12-06

申请人： Florent Begon ,  Vladimir Vasekin ,  Andrew Christophe Rose ,  Nicolas Chaussade

发明人： Florent Begon ,  Vladimir Vasekin ,  Andrew Christophe Rose ,  Nicolas Chaussade

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0802 ,  G06F2212/601

摘要： An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.

摘要翻译： 集成电路2设置有高速缓冲存储器6和高速缓存控制器10，高速缓存控制器10经由高速缓存存储器接口8耦合到高速缓存存储器6.高速缓存控制器支持不同的高速缓冲存储器大小。 高速缓存存储器6包括响应于高速缓存存储器大小信号的掩蔽逻辑14，以形成用于访问高速缓冲存储器6的掩蔽地址值。高速缓存控制器10可以是处理器核心4的一部分，处理器核心4可以在其设计中硬化并且能够 以应对可变高速缓冲存储器大小，因为屏蔽逻辑14被提供在处理器核心4的硬化外围之外的高速缓冲存储器6内。

公开(公告)号：US20070150640A1

公开(公告)日：2007-06-28

申请号：US11634253

申请日：2006-12-06

申请人： Florent Begon ,  Vladimir Vasekin ,  Andrew Christophe Rose ,  Nicolas Chaussade

发明人： Florent Begon ,  Vladimir Vasekin ,  Andrew Christophe Rose ,  Nicolas Chaussade

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F2212/601

摘要： An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.

摘要翻译： 集成电路2具有高速缓冲存储器6和高速缓存控制器10，高速缓冲存储器控制器10通过高速缓存存储器接口8耦合到高速缓冲存储器6。 缓存控制器支持不同的缓存内存大小。 缓存存储器6包括响应于高速缓冲存储器大小信号的掩蔽逻辑14，以形成用于访问高速缓冲存储器6的掩蔽地址值。 高速缓存控制器10可以是处理器核心4的一部分，其可以在其设计中硬化，并且能够应对可变高速缓存存储器大小，因为屏蔽逻辑14被提供在处理器核心的硬化外围之外的高速缓存存储器6内 4。

公开(公告)号：US08769251B2

公开(公告)日：2014-07-01

申请号：US11637948

申请日：2006-12-13

申请人： Philippe Luc ,  Norbert Bernard Eugéne Lataille ,  Florent Begon ,  Nicolas Chaussade

发明人： Philippe Luc ,  Norbert Bernard Eugéne Lataille ,  Florent Begon ,  Nicolas Chaussade

IPC分类号： G06F7/00 ,  G06F15/00

CPC分类号： G06F9/30025 ,  G06F9/30032 ,  G06F9/3824

摘要： A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided for receiving a block of data containing at least one data value, and for converting each data value from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first size, in order to produce re-ordered data. Second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format.

摘要翻译： 提供了一种数据处理装置和方法，用于将数据值从第一端格式转换成第二端格式。 提供了用于接收包含至少一个数据值的数据块，并且将每个数据值从第一个末端格式转换成第二个末端格式的旋转电路。 所述交换电路包括用于对所述数据块执行重新排序操作的第一交换电路，其假定其中包含的所述至少一个数据值具有第一大小，以便产生重新排序的数据。 提供了第二调频电路，其响应于至少一个数据值具有与第一尺寸不同的尺寸的指示，以对已重新排序的数据执行附加的重新排序操作，其中至少考虑到至少 一个数据值，以便将每个数据值转换为第二个末端格式。

公开(公告)号：US07568072B2

公开(公告)日：2009-07-28

申请号：US11513352

申请日：2006-08-31

申请人： Florent Begon ,  Philippe Luc ,  Elodie Charra ,  Nicolas Chaussade

发明人： Florent Begon ,  Philippe Luc ,  Elodie Charra ,  Nicolas Chaussade

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0859 ,  Y02D10/13

摘要： A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information. If it is determined that the data entry should be written to the memory, the eviction logic (1) transfers the information from the eviction buffer to a bus coupled with the memory, (2)transfers data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, (3) transfers information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data portion of the eviction buffer corresponds to the first of the plurality of data entries and the information stored by the data portion of the eviction buffer corresponds to the second of the plurality of data entries, and (4) transfers the data stored by the data portion of the eviction buffer to the bus. This approach provides a low-power, high performance technique for handling eviction requests.

摘要翻译： 一种方法和数据处理装置，包括具有多个数据条目的高速缓存; 驱逐缓冲器，包括信息部分和数据部分; 以及驱逐逻辑，用于将与所述多个数据条目中的第一数据条目相关联的信息从所述高速缓存传送到所述信息部分，并且参考所述信息来确定所述多个数据条目中的第一条数据条目是否应通过检查被写入存储器 信息。 如果确定数据输入应被写入存储器，驱逐逻辑（1）将信息从驱逐缓冲器传送到与存储器耦合的总线，（2）传送多个数据条目中的第一个的数据 从高速缓存到驱逐缓冲器的数据部分，（3）将与多个数据条目中的第二数据条目相关联的信息从高速缓存传送到驱逐缓冲器的关联部分，使得由驱逐的数据部分存储的数据 缓冲器对应于多个数据条目中的第一个，并且由驱逐缓冲器的数据部分存储的信息对应于多个数据条目中的第二数据条目，并且（4）传送由驱逐缓冲器的数据部分存储的数据 到公共汽车 这种方法提供了一种低功耗，高性能的处理驱逐要求的技术。

公开(公告)号：US20080059722A1

公开(公告)日：2008-03-06

申请号：US11513351

申请日：2006-08-31

申请人： Elodie Charra ,  Nicolas Chaussade ,  Philippe Luc ,  Florent Begon

发明人： Elodie Charra ,  Nicolas Chaussade ,  Philippe Luc ,  Florent Begon

IPC分类号： G06F13/00

CPC分类号： G06F13/4036 ,  G06F9/505 ,  G06F2209/5013

摘要： A data processing apparatus and method which handle data processing requests is disclosed. The data processing apparatus comprises: reception logic operable to receive, for subsequent issue, a request to perform a processing activity; response logic operable to receive an indication of whether the data processing apparatus is currently able, if the request was issued, perform the processing activity in response to that issued request; and optimisation logic operable, in the event that the response logic indicates that the data processing apparatus would be currently unable to perform the processing activities in response to the issued request, to alter pending requests received by the reception logic to improve the performance of the data processing apparatus. Accordingly, the time available whilst waiting for unit to become available can be utilised to analyse the pending requests and to optimize or alter these requests in some way in order to subsequently improve the performance of the data processing apparatus. Hence, once the component is then able to deal with the altered requests, the altered requests will then enable the data processing apparatus to operate more efficiently than had the original requests been used.

摘要翻译： 公开了一种处理数据处理请求的数据处理装置和方法。 数据处理装置包括：接收逻辑，可操作以接收执行处理活动的请求，用于随后的发行; 响应逻辑可操作以接收关于数据处理设备当前是否能够的指示，如果请求被发出，则响应于该发出的请求执行处理活动; 并且优化逻辑可操作，如果所述响应逻辑指示所述数据处理装置当前将不能响应所发出的请求执行所述处理活动，则改变由所述接收逻辑接收的未决请求以提高所述数据的性能 处理装置。 因此，可以利用等待单元变得可用的时间来分析待处理的请求并以某种方式优化或改变这些请求，以便随后改进数据处理装置的性能。 因此，一旦组件然后能够处理改变的请求，则改变的请求将使得数据处理装置能够比原始请求被使用更有效率地进行操作。

公开(公告)号：US20080059705A1

公开(公告)日：2008-03-06

申请号：US11512396

申请日：2006-08-30

申请人： Florent Begon ,  Nicolas Chaussade ,  Elodie Charra ,  Philippe Luc

发明人： Florent Begon ,  Nicolas Chaussade ,  Elodie Charra ,  Philippe Luc

IPC分类号： G06F12/00

CPC分类号： G06F12/0859

摘要： A line fill method, line fill unit and data processing apparatus are disclosed. The line fill method, comprises the steps of: a) associating a line fill buffer with a unique identifier; b) initiating a line fill request to provide said line fill buffer with line fill data, said line fill request having said unique identifier associated therewith; and c) in the event that said line fill buffer is filled with said line fill data prior to said line fill data having been returned in response to said line fill request, associating said line fill buffer with a different unique identifier to enable a subsequent line fill request to be initiated. By enabling the line fill buffer to be associated with different unique identifiers, the line fill buffer can initiate a new request despite the previous request not having been completed without there being any concern that the returned data may be misallocated. This enables multiple line fill requests to be simultaneously pending and subsequent line fill requests to be initiated whilst previous line fill requests are outstanding. Accordingly, subsequent line fill requests may be initiated earlier than would have been possible had the line fill buffer had to wait for all of the line fill data associated with each line fill request to be returned.

摘要翻译： 公开了线填充方法，线填充单元和数据处理装置。 行填充方法包括以下步骤：a）将行填充缓冲器与唯一标识符相关联; b）启动线填充请求以向所述线填充缓冲器提供线填充数据，所述线填充请求具有与其相关联的所述唯一标识符; 以及c）在所述行填充缓冲器在所述行填充数据已被响应于所述行填充请求返回之前，用所述行填充数据填充的情况下，将所述行填充缓冲器与不同的唯一标识符相关联以使得后续行 填写请求启动。 通过使行填充缓冲区能够与不同的唯一标识符相关联，即使先前的请求未被完成，行填充缓冲器也可以启动新的请求，而不用担心返回的数据可能被错位。 这使得多个线填充请求同时处于待决状态，并且在先前的行填充请求未完成时启动后续的行填充请求。 因此，如果行填充缓冲器必须等待与每个行填充请求相关联的所有行填充数据被返回，则可以提前开始后续的行填充请求。

公开(公告)号：US07600077B2

公开(公告)日：2009-10-06

申请号：US11651620

申请日：2007-01-10

申请人： Philippe Luc ,  Florent Begon ,  Elodie Charra ,  Nicolas Chaussade

发明人： Philippe Luc ,  Florent Begon ,  Elodie Charra ,  Nicolas Chaussade

IPC分类号： G06F13/00

CPC分类号： G06F12/0804 ,  G06F12/0897 ,  G06F12/1027

摘要： Cache circuitry, a data processing apparatus including such cache circuitry, and a method of handling write requests within cache circuitry, are provided. The cache circuitry has a plurality of slots, with each slot arranged to store attributes associated with a pending access request. A record of identifiers that are available to associate with pending access requests is maintained, and control circuitry is responsive to an access request issued by a device to accept that access request as a pending access request by allocating one of the slots to that access request, obtaining one of said identifiers from the record to associate with that access request, and causing the attributes associated with that access request to be stored in the allocated slot along with the obtained identifier. A check procedure is performed to determine, for each pending access request, whether that access request is allowed to proceed. For a speculative pending write access request that is determined to be allowed to proceed, the attributes associated with that access request and the identifier associated with that access request are transferred from the allocated slot to a write entry within a write access buffer, after which the allocated slot is freed for allocation to a subsequent access request. When a speculative confirmed signal is then received from the device specifying that identifier, the write access buffer outputs the attributes from the write entry to store circuitry used to complete the access request. This provides a very efficient mechanism for handling speculative write accesses within a cache.

摘要翻译： 提供了缓存电路，包括这种高速缓存电路的数据处理设备，以及处理高速缓存电路内的写请求的方法。 高速缓存电路具有多个时隙，每个时隙被布置成存储与待处理的接入请求相关联的属性。 维持可用于与未决访问请求相关联的标识符的记录，并且控制电路响应于由设备发出的访问请求，以将该访问请求作为未决访问请求来分配其中一个时隙给该访问请求， 从所述记录中获取所述标识符之一以与所述访问请求相关联，并且将与所述访问请求相关联的属性与所获得的标识符一起存储在所分配的时隙中。 执行检查过程，以确定对于每个未决访问请求，是否允许该访问请求继续进行。 对于被确定为允许继续进行的推测性待决写入访问请求，与该访问请求相关联的属性和与该访问请求相关联的标识符从分配的时隙转移到写访问缓冲器内的写入条目，之后 分配的时隙被释放以分配给后续的访问请求。 当从指定该标识符的设备接收到推测确认的信号时，写入访问缓冲器从写入条目输出属性以存储用于完成访问请求的存储电路。 这提供了一种处理高速缓存中的推测性写入访问的非常有效的机制。

公开(公告)号：US07552285B2

公开(公告)日：2009-06-23

申请号：US11512396

申请日：2006-08-30

申请人： Florent Begon ,  Nicolas Chaussade ,  Elodie Charra ,  Philippe Luc

发明人： Florent Begon ,  Nicolas Chaussade ,  Elodie Charra ,  Philippe Luc

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0859

摘要： A line fill method, line fill unit and data processing apparatus are disclosed. The line fill method, comprises the steps of: a) associating a line fill buffer with a unique identifier; b) initiating a line fill request to provide said line fill buffer with line fill data, said line fill request having said unique identifier associated therewith; and c) in the event that said line fill buffer is filled with said line fill data prior to said line fill data having been returned in response to said line fill request, associating said line fill buffer with a different unique identifier to enable a subsequent line fill request to be initiated. By enabling the line fill buffer to be associated with different unique identifiers, the line fill buffer can initiate a new request despite the previous request not having been completed without there being any concern that the returned data may be misallocated. This enables multiple line fill requests to be simultaneously pending and subsequent line fill requests to be initiated whilst previous line fill requests are outstanding. Accordingly, subsequent line fill requests may be initiated earlier than would have been possible had the line fill buffer had to wait for all of the line fill data associated with each line fill request to be returned.

摘要翻译： 公开了线填充方法，线填充单元和数据处理装置。 行填充方法包括以下步骤：a）将行填充缓冲器与唯一标识符相关联; b）启动线填充请求以向所述线填充缓冲器提供线填充数据，所述线填充请求具有与其相关联的所述唯一标识符; 以及c）在所述行填充缓冲器在所述行填充数据已被响应于所述行填充请求返回之前，用所述行填充数据填充的情况下，将所述行填充缓冲器与不同的唯一标识符相关联以使得后续行 填写请求启动。 通过使行填充缓冲区能够与不同的唯一标识符相关联，即使先前的请求未被完成，行填充缓冲器也可以启动新的请求，而不用担心返回的数据可能被错位。 这使得多个线填充请求同时处于待决状态，并且在先前的行填充请求未完成时启动后续的行填充请求。 因此，如果行填充缓冲器必须等待与每个行填充请求相关联的所有行填充数据被返回，则可以提前开始后续的行填充请求。

公开(公告)号：US20080148029A1

公开(公告)日：2008-06-19

申请号：US11637948

申请日：2006-12-13

申请人： Philippe Luc ,  Norbert Bernard Eugene Lataille ,  Florent Begon ,  Nicolas Chaussade

发明人： Philippe Luc ,  Norbert Bernard Eugene Lataille ,  Florent Begon ,  Nicolas Chaussade

IPC分类号： G06F9/30

CPC分类号： G06F9/30025 ,  G06F9/30032 ,  G06F9/3824

摘要： A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided within the data processing apparatus for receiving a block of data containing at least one data value, and for converting each data value in the block from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first predetermined size, in order to produce re-ordered data. Further, second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first predetermined size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format. The swizzle circuitry is responsive to an indication that the at least one data value is of the first predetermined size to output the re-ordered data produced by the first swizzle circuitry, whereas otherwise the swizzle circuitry outputs the data produced by the second swizzle circuitry. This can reduce the complexity of swizzle circuitry provided on a critical path, by optimising the swizzle circuitry to handle endian conversion for data values of the first predetermined size, at the expense of data values that are of other sizes requiring more time for the endian conversion operation to be completed.

摘要翻译： 提供了一种数据处理装置和方法，用于将数据值从第一端格式转换成第二端格式。 在数据处理装置内设置有旋转电路，用于接收包含至少一个数据值的数据块，并将该块中的每个数据值从第一端格式转换为第二端格式。 所述交换电路包括用于对所述数据块执行重新排序操作的第一交换电路，其假设其中包含的所述至少一个数据值具有第一预定大小，以便产生重新排序的数据。 此外，提供了第二旋转电路，其响应于至少一个数据值具有不同于第一预定大小的大小的指示，以对已重新排序的数据执行额外的重新排序操作，其中考虑到 所述至少一个数据值以将每个数据值转换为第二端格式。 交换电路响应于至少一个数据值具有第一预定大小的指示，以输出由第一开关电路产生的重新排序的数据，而否则该转换电路输出由第二开关电路产生的数据。 这可以降低在关键路径上提供的交换电路的复杂性，通过优化旋转电路以处理第一预定大小的数据值的端序转换，代价是需要更多时间用于端序转换的其他大小的数据值 操作完成。

公开(公告)号：US20080059713A1

公开(公告)日：2008-03-06

申请号：US11513352

申请日：2006-08-31

申请人： Florent Begon ,  Philippe Luc ,  Elodie Charra ,  Nicolas Chaussade

发明人： Florent Begon ,  Philippe Luc ,  Elodie Charra ,  Nicolas Chaussade

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0859 ,  Y02D10/13

摘要： The present invention provides a method and data processing apparatus comprising: a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic operable to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information, the eviction logic being further operable, if it is determined that the data entry should be written to the memory, to transfer the information from the eviction buffer to a bus coupled with the memory and to transfer data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, to transfer information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data portion of the eviction buffer corresponds to the first of the plurality of data entries and the information stored by the data portion of the eviction buffer corresponds to the second of the plurality of data entries, and to transfer the data stored by the data portion of the eviction buffer to the bus. This approach provides a low-power, high performance technique for handling eviction requests.

摘要翻译： 本发明提供一种方法和数据处理装置，包括：具有多个数据条目的高速缓存; 驱逐缓冲器，包括信息部分和数据部分; 以及驱逐逻辑，可操作以将与所述多个数据条目中的第一数据条目相关联的信息从所述高速缓存传送到所述信息部分，并且参考所述信息来确定所述多个数据条目中的第一条数据条目是否应当被写入存储器 检查信息时，驱逐逻辑可进一步操作，如果确定要将数据条目写入存储器，将信息从驱逐缓冲器传送到与存储器耦合的总线，并传送第一个数据 从高速缓存到驱逐缓冲器的数据部分的多个数据条目，将与多个数据条目中的第二数据条目相关联的信息从高速缓存传送到驱逐缓冲器的关联部分，使得由数据部分存储的数据 驱逐缓冲器对应于多个数据条目中的第一个，并且由驱逐缓冲器的数据部分存储的信息对应于t 他是多个数据条目中的第二个，并且将由驱逐缓冲器的数据部分存储的数据传送到总线。 这种方法提供了一种低功耗，高性能的处理驱逐要求的技术。