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    Method and apparatus for aggregating input data streams
    1.
    发明授权
    Method and apparatus for aggregating input data streams 有权

    公开(公告)号：US09338100B2

    公开(公告)日：2016-05-10

    申请号：US13925564

    申请日：2013-06-24

    申请人： Foundry Networks, LLC

    发明人： Yuen Fai Wong ,  Yu-Mei Lin ,  Richard A. Grenier

    IPC分类号： H04L12/851 ,  H04L12/935 ,  H04L12/931 ,  H04L12/865

    CPC分类号： H04L47/2433 ,  H04L47/6275 ,  H04L49/30 ,  H04L49/352

    摘要： A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.

    BACKPLANE INTERFACE ADAPTER WITH ERROR CONTROL AND REDUNDANT FABRIC
    2.
    发明申请
    BACKPLANE INTERFACE ADAPTER WITH ERROR CONTROL AND REDUNDANT FABRIC 有权
    带有错误控制和冗余织物的背板接口适配器

    公开(公告)号：US20140133488A1

    公开(公告)日：2014-05-15

    申请号：US14075331

    申请日：2013-11-08

    申请人： Foundry Networks, LLC

    发明人： Ronak Patel ,  Ming G. Wong ,  Yu-Mei Lin ,  Andrew Chang ,  Yuen Fai Wong

    IPC分类号： H04L12/741

    CPC分类号： H04L45/74 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/153 ,  H04L49/1538 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3063 ,  H04L49/352 ,  H04L49/90 ,  H04L49/901

    摘要： A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

    摘要翻译： 具有错误控制和冗余结构的背板接口适配器，用于高性能网络交换机。 错误控制可以由包括电平监视器，条带同步错误检测器，流量控制器和控制字符存在跟踪器的管理模块来提供。 背板接口适配器的冗余结构收发器改善了适配器正确和一致地接收携带数据分组的窄输入单元并向交换结构输出宽条带单元的能力。

    METHOD AND APPARATUS FOR AGGREGATING INPUT DATA STREAMS
    3.
    发明申请
    METHOD AND APPARATUS FOR AGGREGATING INPUT DATA STREAMS 有权
    用于聚合输入数据流的方法和装置

    公开(公告)号：US20140153389A1

    公开(公告)日：2014-06-05

    申请号：US13925564

    申请日：2013-06-24

    申请人： Foundry Networks, LLC

    发明人： Yuen Fai Wong ,  Yu-Mei Lin ,  Richard A. Grenier

    IPC分类号： H04L12/851 ,  H04L12/865

    CPC分类号： H04L47/2433 ,  H04L47/6275 ,  H04L49/30 ,  H04L49/352

    摘要： A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.

    摘要翻译： 一种方法和装置将来自第一处理器的多个输入数据流聚合成用于第二处理器的一个数据流，该电路和第一和第二处理器设置在电子电路基板上。 聚合电路包括（a）多个入口数据端口，每个入口数据端口适于从相应的第一处理器接收输入数据流，每个输入数据流由入口数据分组形成，每个入口数据分组包括其中编码的优先级因子 ，（b）耦合到所述入口数据端口的聚合模块，适于响应于所述优先级因素分析并组合所述多个输入数据流到一个聚合数据流中;（c）耦合到所述聚合模块的存储器，适于 存储分析的数据分组，以及（d）耦合到聚合模块的输出数据端口，适于将聚合的数据流输出到第二处理器。

    Backplane Interface Adapter with Error Control and Redundant Fabric
    6.
    发明申请
    Backplane Interface Adapter with Error Control and Redundant Fabric 审中-公开
    具有错误控制和冗余结构的背板接口适配器

    公开(公告)号：US20140023086A1

    公开(公告)日：2014-01-23

    申请号：US13939730

    申请日：2013-07-11

    申请人： Foundry Networks, LLC

    发明人： Ronak Patel ,  Ming G. Wong ,  Yu-Mei Lin ,  Andrew Chang ,  Yuen Fai Wong

    IPC分类号： H04L12/879

    CPC分类号： H04L45/74 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/153 ,  H04L49/1538 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3063 ,  H04L49/352 ,  H04L49/90 ,  H04L49/901

    摘要： A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

    摘要翻译： 具有错误控制和冗余结构的背板接口适配器，用于高性能网络交换机。 错误控制可以由包括电平监视器，条带同步错误检测器，流量控制器和控制字符存在跟踪器的管理模块来提供。 背板接口适配器的冗余结构收发器改善了适配器正确和一致地接收携带数据分组的窄输入单元并向交换结构输出宽条带单元的能力。