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    Backplane Interface Adapter with Error Control and Redundant Fabric
    4.
    发明申请
    Backplane Interface Adapter with Error Control and Redundant Fabric 审中-公开
    具有错误控制和冗余结构的背板接口适配器

    公开(公告)号：US20140023086A1

    公开(公告)日：2014-01-23

    申请号：US13939730

    申请日：2013-07-11

    申请人： Foundry Networks, LLC

    发明人： Ronak Patel ,  Ming G. Wong ,  Yu-Mei Lin ,  Andrew Chang ,  Yuen Fai Wong

    IPC分类号： H04L12/879

    CPC分类号： H04L45/74 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/153 ,  H04L49/1538 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3063 ,  H04L49/352 ,  H04L49/90 ,  H04L49/901

    摘要： A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

    摘要翻译： 具有错误控制和冗余结构的背板接口适配器，用于高性能网络交换机。 错误控制可以由包括电平监视器，条带同步错误检测器，流量控制器和控制字符存在跟踪器的管理模块来提供。 背板接口适配器的冗余结构收发器改善了适配器正确和一致地接收携带数据分组的窄输入单元并向交换结构输出宽条带单元的能力。

    System and method for high speed packet transmission
    5.
    发明授权
    System and method for high speed packet transmission 有权
    高速数据包传输的系统和方法

    公开(公告)号：US09461940B2

    公开(公告)日：2016-10-04

    申请号：US14326859

    申请日：2014-07-09

    申请人： Foundry Networks, LLC

    发明人： Yuen Fai Wong

    IPC分类号： H04L12/28 ,  H04L12/931 ,  H04L12/46 ,  H04L12/743 ,  H04L12/935 ,  H04Q11/04 ,  H04L5/14 ,  H04L12/741

    CPC分类号： H04L49/352 ,  H04L5/14 ,  H04L12/4645 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/30 ,  H04L49/3063 ,  H04Q11/0428

    摘要： The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

    摘要翻译： 本发明提供了用于在一个或多个源设备与一个或多个目的地设备之间提供超过每秒10吉比特的数据传输速度的系统和方法。 根据一个实施例，本发明的系统包括第一和第二媒体访问控制（MAC）接口，以便于在相关联的一组物理接口上接收和传输分组。 该系统还考虑了耦合到MAC接口和相关联的第一和第二存储器结构的第一和第二现场可编程门阵列（FPGA），第一和第二FPGA被配置为执行从第一和第二MAC接口接收的分组的初始处理 并且调度分组到第一和第二MAC接口的传输以传输到一个或多个目的地设备。 第一和第二FPGA进一步操作以分派和从第一和第二存储器结构检索数据包。 耦合到第一和第二存储器结构和背板的第三FPGA可操作以从第一和第二存储器结构检索和分配分组，计算分组的适当目的地并组织用于传输的分组。 第三个FPGA进一步操作以从背板接收和分发分组。

    Techniques for processing incoming failure detection protocol packets
    7.
    发明授权
    Techniques for processing incoming failure detection protocol packets 有权

    公开(公告)号：US09112780B2

    公开(公告)日：2015-08-18

    申请号：US13766330

    申请日：2013-02-13

    申请人： Foundry Networks, LLC

    发明人： Yuen Wong ,  Pedman Moobed

    IPC分类号： H04L12/26 ,  H04L12/24

    CPC分类号： H04L43/0823 ,  H04L41/0631

    摘要： Techniques that assist in processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, only a subset of FDP packets received by the network device is forwarded to the CPU for processing, the other FDP packets are dropped and not forwarded to the CPU. In this manner, the amount of processing that a CPU of the network device has to perform for incoming FDP packets is reduced. This enables the network device to support newer FDPs with shorter periodic interval requirements.

    SYSTEM AND METHOD FOR HIGH SPEED PACKET TRANSMISSION
    8.
    发明申请
    SYSTEM AND METHOD FOR HIGH SPEED PACKET TRANSMISSION 有权
    用于高速分组传输的系统和方法

    公开(公告)号：US20150078211A1

    公开(公告)日：2015-03-19

    申请号：US14326859

    申请日：2014-07-09

    申请人： Foundry Networks, LLC

    发明人： Yuen Fai Wong

    IPC分类号： H04L12/931 ,  H04L5/14 ,  H04L12/741 ,  H04L12/935

    CPC分类号： H04L49/352 ,  H04L5/14 ,  H04L12/4645 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/30 ,  H04L49/3063 ,  H04Q11/0428

    摘要： The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

    摘要翻译： 本发明提供了用于在一个或多个源设备与一个或多个目的地设备之间提供超过每秒10吉比特的数据传输速度的系统和方法。 根据一个实施例，本发明的系统包括第一和第二媒体访问控制（MAC）接口，以便于在相关联的一组物理接口上接收和传输分组。 该系统还考虑了耦合到MAC接口和相关联的第一和第二存储器结构的第一和第二现场可编程门阵列（FPGA），第一和第二FPGA被配置为执行从第一和第二MAC接口接收的分组的初始处理 并且调度分组到第一和第二MAC接口的传输以传输到一个或多个目的地设备。 第一和第二FPGA进一步操作以分派和从第一和第二存储器结构检索数据包。 耦合到第一和第二存储器结构和背板的第三FPGA可操作以从第一和第二存储器结构检索和分配分组，计算分组的适当目的地并组织用于传输的分组。 第三个FPGA进一步操作以从背板接收和分发分组。

    Flow control for multi-hop networks
    9.
    发明授权
    Flow control for multi-hop networks 有权
    多跳网络的流量控制

    公开(公告)号：US08811171B2

    公开(公告)日：2014-08-19

    申请号：US13944876

    申请日：2013-07-17

    申请人： Foundry Networks, LLC

    发明人： Nitin Jain

    IPC分类号： H04L12/28 ,  H04L12/46 ,  H04L12/56

    CPC分类号： H04L47/12 ,  H04L12/2852 ,  H04L12/4675 ,  H04L47/10 ,  H04L47/11 ,  H04L47/2433 ,  H04L47/266

    摘要： Solutions are provided that allow a network device to apply flow control on the MAC layer while taking into account the priority of the frame of traffic. This may be accomplished by generating a frame indicating that traffic flow should be paused, while utilizing a new opcode value, or alternatively by utilizing a new type/length value (possibly combined with a new opcode value). A receiving device may then examine the fields of the frame to determine whether it should use priority-based pausing, and then examine other fields to determine which priority-levels to pause and for how long. This allows for improved efficiency in flow control at the MAC layer. Additionally, the tagged pause frames can be forwarded over multiple hops on Local Area Networks across a Metropolitan Area Network or Wide Area Network.

    摘要翻译： 提供的解决方案允许网络设备在考虑到流量帧的优先级的情况下对MAC层应用流量控制。 这可以通过生成指示业务流应该被暂停，同时利用新的操作码值，或者通过利用新的类型/长度值（可能与新的操作码值组合）来实现。 然后，接收设备可以检查帧的字段以确定它是否应该使用基于优先级的暂停，然后检查其他字段以确定要暂停的优先级等级以及多长时间。 这样可以提高MAC层的流量控制效率。 此外，标记的暂停帧可以通过城域网或广域网在局域网上的多跳进行转发。

    METHODS AND APPARATUS FOR HANDLING WIRELESS ROAMING AMONG AND ACROSS WIRELESS AREA NETWORKS
    10.
    发明申请
    METHODS AND APPARATUS FOR HANDLING WIRELESS ROAMING AMONG AND ACROSS WIRELESS AREA NETWORKS 审中-公开
    用于处理无线区域网络的无线漫游的方法和装置

    公开(公告)号：US20140187241A1

    公开(公告)日：2014-07-03

    申请号：US14202296

    申请日：2014-03-10

    申请人： Foundry Networks, LLC

    发明人： Vishal Sinha

    IPC分类号： H04W8/14

    CPC分类号： H04W8/14 ,  H04W8/02 ,  H04W8/065 ,  H04W8/087 ,  H04W80/04 ,  H04W84/12

    摘要： Wireless roaming in a computer network may be handled through a solution provided on one or more switches in the network. A roam request sent by a switch corresponding to the user's new location may be received by the other switches in the network. If the user is known to any of these switches, then they may execute steps to accommodate the roaming. The tasks performed may vary based on whether the roaming is on layer 2 or layer 3, whether the switch is a home agent for the client, and/or whether the switch already corresponds to the user's new location.

    摘要翻译： 可以通过在网络中的一个或多个交换机上提供的解决方案来处理计算机网络中的无线漫游。 由与用户新位置相对应的交换机发送的漫游请求可以由网络中的其他交换机接收。 如果用户对这些交换机中的任何一个都是已知的，则它们可以执行步骤来适应漫游。 执行的任务可以基于漫游在层2或层3上，交换机是否是客户端的归属代理以及/或交换机是否已经对应于用户的新位置而变化。